Loading arch/arm/mach-mx25/clock.c +12 −2 Original line number Diff line number Diff line Loading @@ -139,6 +139,11 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } static unsigned long get_rate_csi(struct clk *clk) { return get_rate_per(0); } static unsigned long get_rate_otg(struct clk *clk) { unsigned long cctl = readl(CRM_BASE + CCM_CCTL); Loading Loading @@ -211,6 +216,8 @@ DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); Loading @@ -232,6 +239,7 @@ DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ Loading Loading @@ -269,6 +277,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) }; Loading @@ -284,8 +293,9 @@ int __init mx25_clocks_init(void) __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); /* Clock source for lcdc is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); /* Clock source for lcdc and csi is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), CRM_BASE + 0x64); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); Loading arch/arm/mach-mx25/devices.c +22 −0 Original line number Diff line number Diff line Loading @@ -571,3 +571,25 @@ struct platform_device imx_ssi_device1 = { .num_resources = ARRAY_SIZE(imx_ssi_resources1), .resource = imx_ssi_resources1, }; static struct resource mx25_csi_resources[] = { { .start = MX25_CSI_BASE_ADDR, .end = MX25_CSI_BASE_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, { .start = MX25_INT_CSI, .flags = IORESOURCE_IRQ }, }; struct platform_device mx25_csi_device = { .name = "mx2-camera", .id = 0, .num_resources = ARRAY_SIZE(mx25_csi_resources), .resource = mx25_csi_resources, .dev = { .coherent_dma_mask = 0xffffffff, }, }; arch/arm/mach-mx25/devices.h +1 −0 Original line number Diff line number Diff line Loading @@ -25,3 +25,4 @@ extern struct platform_device mxc_wdt; extern struct platform_device mx25_kpp_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device mx25_csi_device; arch/arm/plat-mxc/include/mach/mx25.h +2 −0 Original line number Diff line number Diff line Loading @@ -39,9 +39,11 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_OTG_BASE_ADDR 0x53ff4000 #define MX25_CSI_BASE_ADDR 0x53ff8000 #define MX25_INT_SSI2 11 #define MX25_INT_SSI1 12 #define MX25_INT_CSI 17 #define MX25_INT_DRYICE 25 #define MX25_INT_NANDFC 33 #define MX25_INT_LCDC 39 Loading Loading
arch/arm/mach-mx25/clock.c +12 −2 Original line number Diff line number Diff line Loading @@ -139,6 +139,11 @@ static unsigned long get_rate_lcdc(struct clk *clk) return get_rate_per(7); } static unsigned long get_rate_csi(struct clk *clk) { return get_rate_per(0); } static unsigned long get_rate_otg(struct clk *clk) { unsigned long cctl = readl(CRM_BASE + CCM_CCTL); Loading Loading @@ -211,6 +216,8 @@ DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL); DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); Loading @@ -232,6 +239,7 @@ DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ Loading Loading @@ -269,6 +277,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) }; Loading @@ -284,8 +293,9 @@ int __init mx25_clocks_init(void) __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); /* Clock source for lcdc is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); /* Clock source for lcdc and csi is upll */ __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), CRM_BASE + 0x64); mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); Loading
arch/arm/mach-mx25/devices.c +22 −0 Original line number Diff line number Diff line Loading @@ -571,3 +571,25 @@ struct platform_device imx_ssi_device1 = { .num_resources = ARRAY_SIZE(imx_ssi_resources1), .resource = imx_ssi_resources1, }; static struct resource mx25_csi_resources[] = { { .start = MX25_CSI_BASE_ADDR, .end = MX25_CSI_BASE_ADDR + 0xfff, .flags = IORESOURCE_MEM, }, { .start = MX25_INT_CSI, .flags = IORESOURCE_IRQ }, }; struct platform_device mx25_csi_device = { .name = "mx2-camera", .id = 0, .num_resources = ARRAY_SIZE(mx25_csi_resources), .resource = mx25_csi_resources, .dev = { .coherent_dma_mask = 0xffffffff, }, };
arch/arm/mach-mx25/devices.h +1 −0 Original line number Diff line number Diff line Loading @@ -25,3 +25,4 @@ extern struct platform_device mxc_wdt; extern struct platform_device mx25_kpp_device; extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; extern struct platform_device mx25_csi_device;
arch/arm/plat-mxc/include/mach/mx25.h +2 −0 Original line number Diff line number Diff line Loading @@ -39,9 +39,11 @@ #define MX25_LCDC_BASE_ADDR 0x53fbc000 #define MX25_KPP_BASE_ADDR 0x43fa8000 #define MX25_OTG_BASE_ADDR 0x53ff4000 #define MX25_CSI_BASE_ADDR 0x53ff8000 #define MX25_INT_SSI2 11 #define MX25_INT_SSI1 12 #define MX25_INT_CSI 17 #define MX25_INT_DRYICE 25 #define MX25_INT_NANDFC 33 #define MX25_INT_LCDC 39 Loading