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Commit f742a552 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: fix pm init ordering 

Shovel a bit more of the the code into the setup function, and call
it earlier. Otherwise lockdep is unhappy since we cancel the delayed
resume work before it's initialized.

While at it also shovel the pc8 setup code into the same functions.
I wanted to also ditch the header declaration of the hws pc8 functions,
but for unfathomable reasons that stuff is in intel_display.c instead
of intel_pm.c.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71980


Tested-by: default avatarGuo Jinxian <jinxianx.guo@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0d1430a3

drivers/gpu/drm/i915/i915_dma.c

+1 −9
Original line number Diff line number Diff line
@@ -1490,16 +1490,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->uncore.lock);

	spin_lock_init(&dev_priv->mm.object_stat_lock);

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->rps.hw_lock);

	mutex_init(&dev_priv->modeset_restore_lock);



	mutex_init(&dev_priv->pc8.lock);

	dev_priv->pc8.requirements_met = false;

	dev_priv->pc8.gpu_idle = false;

	dev_priv->pc8.irqs_disabled = false;

	dev_priv->pc8.enabled = false;

	dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */

	INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);

	intel_pm_setup(dev);



	intel_display_crc_init(dev);
@@ -1603,7 +1596,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	}



	intel_irq_init(dev);

	intel_pm_init(dev);

	intel_uncore_sanitize(dev);



	/* Try to make sure MCHBAR is enabled before poking at it */

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -1901,9 +1901,7 @@ void i915_queue_hangcheck(struct drm_device *dev); 
void i915_handle_error(struct drm_device *dev, bool wedged);



extern void intel_irq_init(struct drm_device *dev);

extern void intel_pm_init(struct drm_device *dev);

extern void intel_hpd_init(struct drm_device *dev);

extern void intel_pm_init(struct drm_device *dev);



extern void intel_uncore_sanitize(struct drm_device *dev);

extern void intel_uncore_early_sanitize(struct drm_device *dev);

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -821,6 +821,7 @@ void intel_update_sprite_watermarks(struct drm_plane *plane, 
				    uint32_t sprite_width, int pixel_size,

				    bool enabled, bool scaled);

void intel_init_pm(struct drm_device *dev);

void intel_pm_setup(struct drm_device *dev);

bool intel_fbc_enabled(struct drm_device *dev);

void intel_update_fbc(struct drm_device *dev);

void intel_gpu_ips_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/intel_pm.c

+10 −1
Original line number Diff line number Diff line
@@ -6130,10 +6130,19 @@ int vlv_freq_opcode(int ddr_freq, int val) 
	return val;

}



void intel_pm_init(struct drm_device *dev)

void intel_pm_setup(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	mutex_init(&dev_priv->rps.hw_lock);



	mutex_init(&dev_priv->pc8.lock);

	dev_priv->pc8.requirements_met = false;

	dev_priv->pc8.gpu_idle = false;

	dev_priv->pc8.irqs_disabled = false;

	dev_priv->pc8.enabled = false;

	dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */

	INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);

	INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,

			  intel_gen6_powersave_work);

}