Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f6f3b50f authored by Victor Kamensky's avatar Victor Kamensky Committed by Tony Lindgren
Browse files

ARM: OMAP: counter-32k: raw read and write endian fix 



All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.

Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.

Signed-off-by: default avatarVictor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: default avatarTaras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 834cacfb

arch/arm/plat-omap/counter_32k.c

+3 −3
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static void __iomem *sync32k_cnt_reg; 


static u64 notrace omap_32k_read_sched_clock(void)

{

	return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;

	return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;

}



/**
@@ -64,7 +64,7 @@ static void omap_read_persistent_clock(struct timespec *ts) 
	spin_lock_irqsave(&read_persistent_clock_lock, flags);



	last_cycles = cycles;

	cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;

	cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;



	nsecs = clocksource_cyc2ns(cycles - last_cycles,

					persistent_mult, persistent_shift);
@@ -95,7 +95,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) 
	 * The 'SCHEME' bits(30-31) of the revision register is used

	 * to identify the version.

	 */

	if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &

	if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &

						OMAP2_32KSYNCNT_REV_SCHEME)

		sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;

	else