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Commit f6da46a3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

clk: tegra: Remove CLK_IS_ROOT 



This flag is a no-op now. Remove usage of the flag.

Acked-by: default avatarRhyland Klein <rklein@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent afb4bdc9

drivers/clk/tegra/clk-audio-sync.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -72,7 +72,7 @@ struct clk *tegra_clk_register_sync_source(const char *name, 




	init.ops = &tegra_clk_sync_source_ops;

	init.ops = &tegra_clk_sync_source_ops;

	init.name = name;

	init.name = name;

	init.flags = CLK_IS_ROOT;

	init.flags = 0;

	init.parent_names = NULL;

	init.parent_names = NULL;

	init.num_parents = 0;

	init.num_parents = 0;

drivers/clk/tegra/clk-dfll.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -995,7 +995,6 @@ static const struct clk_ops dfll_clk_ops = { 
};

};





static struct clk_init_data dfll_clk_init_data = {

static struct clk_init_data dfll_clk_init_data = {

	.flags		= CLK_IS_ROOT,

	.ops		= &dfll_clk_ops,

	.ops		= &dfll_clk_ops,

	.num_parents	= 0,

	.num_parents	= 0,

};

};

drivers/clk/tegra/clk-tegra-fixed.c

+2 −4
Original line number Original line Diff line number Diff line
@@ -52,8 +52,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, 
		return -EINVAL;

		return -EINVAL;

	}

	}





	osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,

	osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);

				      *osc_freq);





	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);

	if (!dt_clk)

	if (!dt_clk)
@@ -88,8 +87,7 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks) 
	/* clk_32k */

	/* clk_32k */

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);

	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);

	if (dt_clk) {

	if (dt_clk) {

		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,

		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);

					CLK_IS_ROOT, 32768);

		*dt_clk = clk;

		*dt_clk = clk;

	}

	}

drivers/clk/tegra/clk-tegra114.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -972,8 +972,7 @@ static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 
	struct clk *clk;

	struct clk *clk;





	/* clk_32k */

	/* clk_32k */

	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT,

	clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);

				      32768);

	clks[TEGRA114_CLK_CLK_32K] = clk;

	clks[TEGRA114_CLK_CLK_32K] = clk;





	/* clk_m_div2 */

	/* clk_m_div2 */

drivers/clk/tegra/clk-tegra20.c

+4 −6
Original line number Original line Diff line number Diff line
@@ -837,15 +837,13 @@ static void __init tegra20_periph_clk_init(void) 
	clks[TEGRA20_CLK_PEX] = clk;

	clks[TEGRA20_CLK_PEX] = clk;





	/* cdev1 */

	/* cdev1 */

	clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,

	clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000);

				      26000000);

	clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,

	clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0,

				    clk_base, 0, 94, periph_clk_enb_refcnt);

				    clk_base, 0, 94, periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_CDEV1] = clk;

	clks[TEGRA20_CLK_CDEV1] = clk;





	/* cdev2 */

	/* cdev2 */

	clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, CLK_IS_ROOT,

	clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000);

				      26000000);

	clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,

	clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0,

				    clk_base, 0, 93, periph_clk_enb_refcnt);

				    clk_base, 0, 93, periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_CDEV2] = clk;

	clks[TEGRA20_CLK_CDEV2] = clk;
@@ -879,8 +877,8 @@ static void __init tegra20_osc_clk_init(void) 
	input_freq = tegra20_clk_measure_input_freq();

	input_freq = tegra20_clk_measure_input_freq();





	/* clk_m */

	/* clk_m */

	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT |

	clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,

				      CLK_IGNORE_UNUSED, input_freq);

				      input_freq);

	clks[TEGRA20_CLK_CLK_M] = clk;

	clks[TEGRA20_CLK_CLK_M] = clk;





	/* pll_ref */

	/* pll_ref */