Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f6cadc1b authored by Aastha Gupta's avatar Aastha Gupta Committed by Greg Kroah-Hartman
Browse files

staging: rtl8188eu: fix block comment styling in rtl8188eu files 



This patch fixes checkpatch.pl warnings for block comment styling.
1. Block comment use a trailing */ on a separate line.
2. Block comment use * on subsequent lines.
3. Block comment should align * on each line.

Signed-off-by: default avatarAastha Gupta <aastha.gupta4104@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0bb73711

drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h

+22 −11
Original line number Diff line number Diff line
@@ -75,7 +75,8 @@ enum rf_radio_path { 
#define CHANNEL_MAX_NUMBER		14	/*  14 is the max chnl number */

#define MAX_CHNL_GROUP_24G		6	/*  ch1~2, ch3~5, ch6~8,

						 *ch9~11, ch12~13, CH 14

						 * total three groups */

						 * total three groups

						 */

#define CHANNEL_GROUP_MAX_88E		6



enum wireless_mode {
@@ -116,35 +117,45 @@ struct bb_reg_def { 
				/*	0x80c~0x80f [4 bytes] */

	u32 rfHSSIPara1;	/*  wire parameter control1 : */

				/*	0x820~0x823,0x828~0x82b,

				 *	0x830~0x833, 0x838~0x83b [16 bytes] */

				 *	0x830~0x833, 0x838~0x83b [16 bytes]

				 */

	u32 rfHSSIPara2;	/*  wire parameter control2 : */

				/*	0x824~0x827,0x82c~0x82f, 0x834~0x837,

				 *	0x83c~0x83f [16 bytes] */

				 *	0x83c~0x83f [16 bytes]

				 */

	u32 rfSwitchControl;	/* Tx Rx antenna control : */

				/*	0x858~0x85f [16 bytes] */

	u32 rfAGCControl1;	/* AGC parameter control1 : */

				/*	0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,

				 * 0xc68~0xc6b [16 bytes] */

				 * 0xc68~0xc6b [16 bytes]

				 */

	u32 rfAGCControl2;	/* AGC parameter control2 : */

				/*	0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,

				 *	0xc6c~0xc6f [16 bytes] */

				 *	0xc6c~0xc6f [16 bytes]

				 */

	u32 rfRxIQImbalance;	/* OFDM Rx IQ imbalance matrix : */

				/*	0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,

				 *	0xc2c~0xc2f [16 bytes] */

				 *	0xc2c~0xc2f [16 bytes]

				 */

	u32 rfRxAFE;		/* Rx IQ DC ofset and Rx digital filter,

				 * Rx DC notch filter : */

				 * Rx DC notch filter :

				 */

				/*	0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,

				 *	0xc28~0xc2b [16 bytes] */

				 *	0xc28~0xc2b [16 bytes]

				 */

	u32 rfTxIQImbalance;	/* OFDM Tx IQ imbalance matrix */

				/*	0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,

				 *	 0xc98~0xc9b [16 bytes] */

				 *	 0xc98~0xc9b [16 bytes]

				 */

	u32 rfTxAFE;		/* Tx IQ DC Offset and Tx DFIR type */

				/*	0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,

				 *	0xc9c~0xc9f [16 bytes] */

				 *	0xc9c~0xc9f [16 bytes]

				 */

	u32 rfLSSIReadBack;	/* LSSI RF readback data SI mode */

				/*	0x8a0~0x8af [16 bytes] */

	u32 rfLSSIReadBackPi;	/* LSSI RF readback data PI mode 0x8b8-8bc for

				 * Path A and B */

				 * Path A and B

				 */

};



/*------------------------------Define structure----------------------------*/

drivers/staging/rtl8188eu/include/Hal8188EPhyReg.h

+2 −1
Original line number Diff line number Diff line
@@ -136,7 +136,8 @@ 
#define	rCCK0_CCA			0xa08



/* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold,

 * RX LNA Threshold useless now. Not the same as 90 series */

 * RX LNA Threshold useless now. Not the same as 90 series

 */

#define	rCCK0_RxAGC1			0xa0c

#define	rCCK0_RxAGC2			0xa10	/* AGC & DAGC */

drivers/staging/rtl8188eu/include/Hal8188ERateAdaptive.h

+14 −14
Original line number Diff line number Diff line 
#ifndef __INC_RA_H

#define __INC_RA_H

/*++

Copyright (c) Realtek Semiconductor Corp. All rights reserved.



Module Name:

	RateAdaptive.h



Abstract:

	Prototype of RA and related data structure.



Major Change History:

	When       Who               What

	---------- ---------------   -------------------------------

	2011-08-12 Page            Create.

--*/

/*

 * Copyright (c) Realtek Semiconductor Corp. All rights reserved.

 *

 * Module Name:

 *	RateAdaptive.h

 *

 * Abstract:

 *	Prototype of RA and related data structure.

 *

 * Major Change History:

 *	When       Who               What

 *	---------- ---------------   -------------------------------

 *	2011-08-12 Page            Create.

 */



/*  Rate adaptive define */

#define	PERENTRY	23

drivers/staging/rtl8188eu/include/basic_types.h

+8 −6
Original line number Diff line number Diff line
@@ -20,7 +20,8 @@ 


/* port from fw */

/*  TODO: Macros Below are Sync from SD7-Driver. It is necessary

 * to check correctness */

 * to check correctness

 */



/*

 *	Call endian free function when
@@ -75,8 +76,9 @@ 
	(EF1BYTE(*((u8 *)(__pstart))))



/* Description:

Translate subfield (continuous bits in little-endian) of 4-byte

value to host byte ordering.*/

 * Translate subfield (continuous bits in little-endian) of 4-byte

 * value to host byte ordering.

 */

#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \

	( \

		(LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \

drivers/staging/rtl8188eu/include/drv_types.h

+2 −1
Original line number Diff line number Diff line
@@ -128,7 +128,8 @@ struct dvobj_priv { 
static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)

{

	/* todo: get interface type from dvobj and the return

	 * the dev accordingly */

	 * the dev accordingly

	 */

	return &dvobj->pusbintf->dev;

};