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Commit f6bba894 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx-next' 



Or Gerlitz says:

====================
Mellanox driver update, Oct 14 2015

This series contains two more patches from Eli, patch from Majd
to support PCI error handlers and a fix from Jack to mlx4 VFs
when probed without a provisioned mac address.

The patch set applied on top of net-next commit bbb300eb "Merge branch 'bridge-vlan'"

changes from V0:
  - made the health flag int --> bool to address comment from Dave on patch #1
  - fixed sparse warning noted by the 0-day build tests in patch #2
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f985c65c 2b3ddf27

drivers/net/ethernet/mellanox/mlx4/en_netdev.c

+11 −12
Original line number Diff line number Diff line
@@ -2816,7 +2816,6 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 
	struct mlx4_en_priv *priv;

	int i;

	int err;

	u64 mac_u64;



	dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),

				 MAX_TX_RINGS, MAX_RX_RINGS);
@@ -2908,17 +2907,17 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 
	dev->addr_len = ETH_ALEN;

	mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);

	if (!is_valid_ether_addr(dev->dev_addr)) {

		if (mlx4_is_slave(priv->mdev->dev)) {

			eth_hw_addr_random(dev);

			en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);

			mac_u64 = mlx4_mac_to_u64(dev->dev_addr);

			mdev->dev->caps.def_mac[priv->port] = mac_u64;

		} else {

		en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",

		       priv->port, dev->dev_addr);

		err = -EINVAL;

		goto out;

		}

	} else if (mlx4_is_slave(priv->mdev->dev) &&

		   (priv->mdev->dev->port_random_macs & 1 << priv->port)) {

		/* Random MAC was assigned in mlx4_slave_cap

		 * in mlx4_core module

		 */

		dev->addr_assign_type |= NET_ADDR_RANDOM;

		en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);

	}



	memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));

drivers/net/ethernet/mellanox/mlx4/fw.c

+16 −0
Original line number Diff line number Diff line
@@ -2840,3 +2840,19 @@ int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 
	return -EOPNOTSUPP;

}

EXPORT_SYMBOL(set_phv_bit);



void mlx4_replace_zero_macs(struct mlx4_dev *dev)

{

	int i;

	u8 mac_addr[ETH_ALEN];



	dev->port_random_macs = 0;

	for (i = 1; i <= dev->caps.num_ports; ++i)

		if (!dev->caps.def_mac[i] &&

		    dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {

			eth_random_addr(mac_addr);

			dev->port_random_macs |= 1 << i;

			dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr);

		}

}

EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs);

drivers/net/ethernet/mellanox/mlx4/main.c

+2 −0
Original line number Diff line number Diff line
@@ -863,6 +863,8 @@ static int mlx4_slave_cap(struct mlx4_dev *dev) 
		return -ENODEV;

	}



	mlx4_replace_zero_macs(dev);



	dev->caps.qp0_qkey = kcalloc(dev->caps.num_ports, sizeof(u32), GFP_KERNEL);

	dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);

	dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);

drivers/net/ethernet/mellanox/mlx4/mlx4.h

+2 −0
Original line number Diff line number Diff line
@@ -1378,6 +1378,8 @@ void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 


void mlx4_init_quotas(struct mlx4_dev *dev);



/* for VFs, replace zero MACs with randomly-generated MACs at driver start */

void mlx4_replace_zero_macs(struct mlx4_dev *dev);

int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);

/* Returns the VF index of slave */

int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);

drivers/net/ethernet/mellanox/mlx5/core/cmd.c

+170 −0
Original line number Diff line number Diff line
@@ -256,8 +256,154 @@ static void dump_buf(void *buf, int size, int data_only, int offset) 


enum {

	MLX5_DRIVER_STATUS_ABORTED = 0xfe,

	MLX5_DRIVER_SYND = 0xbadd00de,

};



static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,

				       u32 *synd, u8 *status)

{

	*synd = 0;

	*status = 0;



	switch (op) {

	case MLX5_CMD_OP_TEARDOWN_HCA:

	case MLX5_CMD_OP_DISABLE_HCA:

	case MLX5_CMD_OP_MANAGE_PAGES:

	case MLX5_CMD_OP_DESTROY_MKEY:

	case MLX5_CMD_OP_DESTROY_EQ:

	case MLX5_CMD_OP_DESTROY_CQ:

	case MLX5_CMD_OP_DESTROY_QP:

	case MLX5_CMD_OP_DESTROY_PSV:

	case MLX5_CMD_OP_DESTROY_SRQ:

	case MLX5_CMD_OP_DESTROY_XRC_SRQ:

	case MLX5_CMD_OP_DESTROY_DCT:

	case MLX5_CMD_OP_DEALLOC_Q_COUNTER:

	case MLX5_CMD_OP_DEALLOC_PD:

	case MLX5_CMD_OP_DEALLOC_UAR:

	case MLX5_CMD_OP_DETTACH_FROM_MCG:

	case MLX5_CMD_OP_DEALLOC_XRCD:

	case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:

	case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:

	case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:

	case MLX5_CMD_OP_DESTROY_TIR:

	case MLX5_CMD_OP_DESTROY_SQ:

	case MLX5_CMD_OP_DESTROY_RQ:

	case MLX5_CMD_OP_DESTROY_RMP:

	case MLX5_CMD_OP_DESTROY_TIS:

	case MLX5_CMD_OP_DESTROY_RQT:

	case MLX5_CMD_OP_DESTROY_FLOW_TABLE:

	case MLX5_CMD_OP_DESTROY_FLOW_GROUP:

	case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:

		return MLX5_CMD_STAT_OK;



	case MLX5_CMD_OP_QUERY_HCA_CAP:

	case MLX5_CMD_OP_QUERY_ADAPTER:

	case MLX5_CMD_OP_INIT_HCA:

	case MLX5_CMD_OP_ENABLE_HCA:

	case MLX5_CMD_OP_QUERY_PAGES:

	case MLX5_CMD_OP_SET_HCA_CAP:

	case MLX5_CMD_OP_QUERY_ISSI:

	case MLX5_CMD_OP_SET_ISSI:

	case MLX5_CMD_OP_CREATE_MKEY:

	case MLX5_CMD_OP_QUERY_MKEY:

	case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:

	case MLX5_CMD_OP_PAGE_FAULT_RESUME:

	case MLX5_CMD_OP_CREATE_EQ:

	case MLX5_CMD_OP_QUERY_EQ:

	case MLX5_CMD_OP_GEN_EQE:

	case MLX5_CMD_OP_CREATE_CQ:

	case MLX5_CMD_OP_QUERY_CQ:

	case MLX5_CMD_OP_MODIFY_CQ:

	case MLX5_CMD_OP_CREATE_QP:

	case MLX5_CMD_OP_RST2INIT_QP:

	case MLX5_CMD_OP_INIT2RTR_QP:

	case MLX5_CMD_OP_RTR2RTS_QP:

	case MLX5_CMD_OP_RTS2RTS_QP:

	case MLX5_CMD_OP_SQERR2RTS_QP:

	case MLX5_CMD_OP_2ERR_QP:

	case MLX5_CMD_OP_2RST_QP:

	case MLX5_CMD_OP_QUERY_QP:

	case MLX5_CMD_OP_SQD_RTS_QP:

	case MLX5_CMD_OP_INIT2INIT_QP:

	case MLX5_CMD_OP_CREATE_PSV:

	case MLX5_CMD_OP_CREATE_SRQ:

	case MLX5_CMD_OP_QUERY_SRQ:

	case MLX5_CMD_OP_ARM_RQ:

	case MLX5_CMD_OP_CREATE_XRC_SRQ:

	case MLX5_CMD_OP_QUERY_XRC_SRQ:

	case MLX5_CMD_OP_ARM_XRC_SRQ:

	case MLX5_CMD_OP_CREATE_DCT:

	case MLX5_CMD_OP_DRAIN_DCT:

	case MLX5_CMD_OP_QUERY_DCT:

	case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:

	case MLX5_CMD_OP_QUERY_VPORT_STATE:

	case MLX5_CMD_OP_MODIFY_VPORT_STATE:

	case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:

	case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:

	case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:

	case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:

	case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:

	case MLX5_CMD_OP_SET_ROCE_ADDRESS:

	case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:

	case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:

	case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:

	case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:

	case MLX5_CMD_OP_QUERY_VPORT_COUNTER:

	case MLX5_CMD_OP_ALLOC_Q_COUNTER:

	case MLX5_CMD_OP_QUERY_Q_COUNTER:

	case MLX5_CMD_OP_ALLOC_PD:

	case MLX5_CMD_OP_ALLOC_UAR:

	case MLX5_CMD_OP_CONFIG_INT_MODERATION:

	case MLX5_CMD_OP_ACCESS_REG:

	case MLX5_CMD_OP_ATTACH_TO_MCG:

	case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:

	case MLX5_CMD_OP_MAD_IFC:

	case MLX5_CMD_OP_QUERY_MAD_DEMUX:

	case MLX5_CMD_OP_SET_MAD_DEMUX:

	case MLX5_CMD_OP_NOP:

	case MLX5_CMD_OP_ALLOC_XRCD:

	case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:

	case MLX5_CMD_OP_QUERY_CONG_STATUS:

	case MLX5_CMD_OP_MODIFY_CONG_STATUS:

	case MLX5_CMD_OP_QUERY_CONG_PARAMS:

	case MLX5_CMD_OP_MODIFY_CONG_PARAMS:

	case MLX5_CMD_OP_QUERY_CONG_STATISTICS:

	case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:

	case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:

	case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:

	case MLX5_CMD_OP_CREATE_TIR:

	case MLX5_CMD_OP_MODIFY_TIR:

	case MLX5_CMD_OP_QUERY_TIR:

	case MLX5_CMD_OP_CREATE_SQ:

	case MLX5_CMD_OP_MODIFY_SQ:

	case MLX5_CMD_OP_QUERY_SQ:

	case MLX5_CMD_OP_CREATE_RQ:

	case MLX5_CMD_OP_MODIFY_RQ:

	case MLX5_CMD_OP_QUERY_RQ:

	case MLX5_CMD_OP_CREATE_RMP:

	case MLX5_CMD_OP_MODIFY_RMP:

	case MLX5_CMD_OP_QUERY_RMP:

	case MLX5_CMD_OP_CREATE_TIS:

	case MLX5_CMD_OP_MODIFY_TIS:

	case MLX5_CMD_OP_QUERY_TIS:

	case MLX5_CMD_OP_CREATE_RQT:

	case MLX5_CMD_OP_MODIFY_RQT:

	case MLX5_CMD_OP_QUERY_RQT:

	case MLX5_CMD_OP_CREATE_FLOW_TABLE:

	case MLX5_CMD_OP_QUERY_FLOW_TABLE:

	case MLX5_CMD_OP_CREATE_FLOW_GROUP:

	case MLX5_CMD_OP_QUERY_FLOW_GROUP:

	case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:

	case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:

		*status = MLX5_DRIVER_STATUS_ABORTED;

		*synd = MLX5_DRIVER_SYND;

		return -EIO;

	default:

		mlx5_core_err(dev, "Unknown FW command (%d)\n", op);

		return -EINVAL;

	}

}



const char *mlx5_command_str(int command)

{

	switch (command) {
@@ -592,6 +738,16 @@ static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent) 
	return err;

}



static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)

{

	return &out->syndrome;

}



static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)

{

	return &out->status;

}



/*  Notes:

 *    1. Callback functions may not sleep

 *    2. page queue commands do not support asynchrous completion
@@ -1200,6 +1356,11 @@ static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size, 
	return msg;

}



static u16 opcode_from_in(struct mlx5_inbox_hdr *in)

{

	return be16_to_cpu(in->opcode);

}



static int is_manage_pages(struct mlx5_inbox_hdr *in)

{

	return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
@@ -1214,6 +1375,15 @@ static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 
	gfp_t gfp;

	int err;

	u8 status = 0;

	u32 drv_synd;



	if (pci_channel_offline(dev->pdev) ||

	    dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {

		err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);

		*get_synd_ptr(out) = cpu_to_be32(drv_synd);

		*get_status_ptr(out) = status;

		return err;

	}



	pages_queue = is_manage_pages(in);

	gfp = callback ? GFP_ATOMIC : GFP_KERNEL;