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Commit f6b0df55 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush 



For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all
related caches (radix__tlb_flush()). Hence the pwc flush is not needed.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 11fe909d

arch/powerpc/mm/tlb-radix.c

+12 −0
Original line number Diff line number Diff line
@@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) 
{

	unsigned long pid;

	struct mm_struct *mm = tlb->mm;

	/*

	 * If we are doing a full mm flush, we will do a tlb flush

	 * with RIC_FLUSH_ALL later.

	 */

	if (tlb->fullmm)

		return;



	preempt_disable();
@@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) 
	unsigned long pid;

	struct mm_struct *mm = tlb->mm;



	/*

	 * If we are doing a full mm flush, we will do a tlb flush

	 * with RIC_FLUSH_ALL later.

	 */

	if (tlb->fullmm)

		return;

	preempt_disable();



	pid = mm->context.id;