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Commit f67dc6d8 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Parametrize TRANS_DP_PORT_SEL 



Parametrize the TRANS_DP_PORT_SEL macros.

v2: WARN for bogus ports (Jani)
    Order the defines mask,value (Jani)

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180518152931.13104-2-ville.syrjala@linux.intel.com
parent f606bc6d

drivers/gpu/drm/i915/i915_reg.h

+3 −5
Original line number Diff line number Diff line
@@ -7887,11 +7887,9 @@ enum { 
#define _TRANS_DP_CTL_C		0xe2300

#define TRANS_DP_CTL(pipe)	_MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)

#define  TRANS_DP_OUTPUT_ENABLE	(1<<31)

#define  TRANS_DP_PORT_SEL_B	(0<<29)

#define  TRANS_DP_PORT_SEL_C	(1<<29)

#define  TRANS_DP_PORT_SEL_D	(2<<29)

#define  TRANS_DP_PORT_SEL_NONE	(3<<29)

#define  TRANS_DP_PORT_SEL_MASK		(3 << 29)

#define  TRANS_DP_PORT_SEL_NONE		(3 << 29)

#define  TRANS_DP_PORT_SEL(port)	(((port) - PORT_B) << 29)

#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)

#define  TRANS_DP_AUDIO_ONLY	(1<<26)

#define  TRANS_DP_ENH_FRAMING	(1<<18)

drivers/gpu/drm/i915/intel_display.c

+8 −16
Original line number Diff line number Diff line
@@ -1360,9 +1360,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 
{

	enum pipe port_pipe;



	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL(PORT_B));

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL(PORT_C));

	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL(PORT_D));



	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&

			port_pipe == pipe,
@@ -4702,6 +4702,8 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) 
			&crtc_state->base.adjusted_mode;

		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;

		i915_reg_t reg = TRANS_DP_CTL(pipe);

		enum port port;



		temp = I915_READ(reg);

		temp &= ~(TRANS_DP_PORT_SEL_MASK |

			  TRANS_DP_SYNC_MASK |
@@ -4714,19 +4716,9 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) 
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)

			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;



		switch (intel_trans_dp_port_sel(crtc)) {

		case PORT_B:

			temp |= TRANS_DP_PORT_SEL_B;

			break;

		case PORT_C:

			temp |= TRANS_DP_PORT_SEL_C;

			break;

		case PORT_D:

			temp |= TRANS_DP_PORT_SEL_D;

			break;

		default:

			BUG();

		}

		port = intel_trans_dp_port_sel(crtc);

		WARN_ON(port < PORT_B || port > PORT_D);

		temp |= TRANS_DP_PORT_SEL(port);



		I915_WRITE(reg, temp);

	}