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Commit f5894539 authored by Fabio Estevam's avatar Fabio Estevam Committed by Mike Turquette
Browse files

clk: mxs: Use a better name for the USB PHY clock 



Use a better name for the USB PHY clock.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 90d4971d

Documentation/devicetree/bindings/clock/imx23-clock.txt

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ clocks and IDs. 
	lcdif		38

	etm		39

	usb		40

	usb_pwr		41

	usb_phy		41



Examples:

Documentation/devicetree/bindings/clock/imx28-clock.txt

+2 −2
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ clocks and IDs. 
	can1		59

	usb0		60

	usb1		61

	usb0_pwr	62

	usb1_pwr	63

	usb0_phy	62

	usb1_phy	63

	enet_out	64



Examples:

drivers/clk/mxs/clk-imx23.c

+3 −3
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ enum imx23_clk { 
	cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,

	emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,

	clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,

	lcdif, etm, usb, usb_pwr,

	lcdif, etm, usb, usb_phy,

	clk_max

};
@@ -143,8 +143,8 @@ int __init mx23_clocks_init(void) 
	clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);

	clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);

	clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);

	clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2);

	clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);

	clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);

	clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);



	for (i = 0; i < ARRAY_SIZE(clks); i++)

		if (IS_ERR(clks[i])) {

drivers/clk/mxs/clk-imx28.c

+5 −5
Original line number Diff line number Diff line
@@ -140,7 +140,7 @@ enum imx28_clk { 
	emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,

	clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,

	ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,

	fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out,

	fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,

	clk_max

};
@@ -218,10 +218,10 @@ int __init mx28_clocks_init(void) 
	clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);

	clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);

	clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);

	clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2);

	clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16);

	clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);

	clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);

	clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);

	clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);

	clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);

	clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);

	clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);



	for (i = 0; i < ARRAY_SIZE(clks); i++)