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Commit f4db43a3 authored by Jaswinder Singh Rajput's avatar Jaswinder Singh Rajput Committed by Ingo Molnar
Browse files

perf_counter, x86: Update AMD hw caching related event table 



All AMD models share the same hw caching related event table.

Also complete the table with more events.

Signed-off-by: default avatarJaswinder Singh Rajput <jaswinderrajput@gmail.com>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <1244835381.2802.2.camel@ht.satnam>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 4d2be126

arch/x86/kernel/cpu/perf_counter.c

+15 −21
Original line number Diff line number Diff line
@@ -389,23 +389,23 @@ static u64 intel_pmu_raw_event(u64 event) 
	return event & CORE_EVNTSEL_MASK;

}



static const u64 amd_0f_hw_cache_event_ids

static const u64 amd_hw_cache_event_ids

				[PERF_COUNT_HW_CACHE_MAX]

				[PERF_COUNT_HW_CACHE_OP_MAX]

				[PERF_COUNT_HW_CACHE_RESULT_MAX] =

{

 [ C(L1D) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

		[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */

		[ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

		[ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */

		[ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */

	},

 },

 [ C(L1I ) ] = {
@@ -418,17 +418,17 @@ static const u64 amd_0f_hw_cache_event_ids 
		[ C(RESULT_MISS)   ] = -1,

	},

	[ C(OP_PREFETCH) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */

		[ C(RESULT_MISS)   ] = 0,

	},

 },

 [ C(LL  ) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

		[ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */

		[ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */

		[ C(RESULT_MISS)   ] = 0,

	},

	[ C(OP_PREFETCH) ] = {
@@ -438,8 +438,8 @@ static const u64 amd_0f_hw_cache_event_ids 
 },

 [ C(DTLB) ] = {

	[ C(OP_READ) ] = {

		[ C(RESULT_ACCESS) ] = 0,

		[ C(RESULT_MISS)   ] = 0,

		[ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */

		[ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */

	},

	[ C(OP_WRITE) ] = {

		[ C(RESULT_ACCESS) ] = 0,
@@ -1465,16 +1465,10 @@ static int amd_pmu_init(void) 


	x86_pmu = amd_pmu;



	switch (boot_cpu_data.x86) {

	case 0x0f:

	case 0x10:

	case 0x11:

		memcpy(hw_cache_event_ids, amd_0f_hw_cache_event_ids,

	/* Events are common for all AMDs */

	memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,

	       sizeof(hw_cache_event_ids));



		pr_cont("AMD Family 0f/10/11 events, ");

		break;

	}

	return 0;

}