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Commit f3f415a3 authored by Alan Cox's avatar Alan Cox Committed by Greg Kroah-Hartman
Browse files

Staging: et131x: CSRAddress to regs 



Switch this to a Linux like naming as it occurs all over.

Signed-off-by: default avatarAlan Cox <alan@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 6ae56042

drivers/staging/et131x/et1310_jagcore.c

+4 −4
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ extern dbg_info_t *et131x_dbginfo; 
 */

void ConfigGlobalRegs(struct et131x_adapter *etdev)

{

	struct _GLOBAL_t __iomem *pGbl = &etdev->CSRAddress->global;

	struct _GLOBAL_t __iomem *pGbl = &etdev->regs->global;



	DBG_ENTER(et131x_dbginfo);
@@ -188,7 +188,7 @@ void ConfigMMCRegs(struct et131x_adapter *etdev) 
	mmc_ctrl.bits.arb_disable = 0x0;

	mmc_ctrl.bits.mmc_enable = 0x1;



	writel(mmc_ctrl.value, &etdev->CSRAddress->mmc.mmc_ctrl.value);

	writel(mmc_ctrl.value, &etdev->regs->mmc.mmc_ctrl.value);



	DBG_LEAVE(et131x_dbginfo);

}
@@ -207,12 +207,12 @@ void et131x_enable_interrupts(struct et131x_adapter *adapter) 
		MaskValue |= 0x10000;



	adapter->CachedMaskValue.value = MaskValue;

	writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);

	writel(MaskValue, &adapter->regs->global.int_mask.value);

}



void et131x_disable_interrupts(struct et131x_adapter *adapter)

{

	/* Disable all global interrupts */

	adapter->CachedMaskValue.value = INT_MASK_DISABLE;

	writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);

	writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask.value);

}

drivers/staging/et131x/et1310_mac.c

+16 −16
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ extern dbg_info_t *et131x_dbginfo; 
 */

void ConfigMACRegs1(struct et131x_adapter *etdev)

{

	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;

	struct _MAC_t __iomem *pMac = &etdev->regs->mac;

	MAC_STATION_ADDR1_t station1;

	MAC_STATION_ADDR2_t station2;

	MAC_IPG_t ipg;
@@ -182,7 +182,7 @@ void ConfigMACRegs1(struct et131x_adapter *etdev) 
void ConfigMACRegs2(struct et131x_adapter *etdev)

{

	int32_t delay = 0;

	struct _MAC_t __iomem *pMac = &etdev->CSRAddress->mac;

	struct _MAC_t __iomem *pMac = &etdev->regs->mac;

	MAC_CFG1_t cfg1;

	MAC_CFG2_t cfg2;

	MAC_IF_CTRL_t ifctrl;
@@ -190,7 +190,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 


	DBG_ENTER(et131x_dbginfo);



	ctl.value = readl(&etdev->CSRAddress->txmac.ctl.value);

	ctl.value = readl(&etdev->regs->txmac.ctl.value);

	cfg1.value = readl(&pMac->cfg1.value);

	cfg2.value = readl(&pMac->cfg2.value);

	ifctrl.value = readl(&pMac->if_ctrl.value);
@@ -269,7 +269,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 
	/* Enable TXMAC */

	ctl.bits.txmac_en = 0x1;

	ctl.bits.fc_disable = 0x1;

	writel(ctl.value, &etdev->CSRAddress->txmac.ctl.value);

	writel(ctl.value, &etdev->regs->txmac.ctl.value);



	/* Ready to start the RXDMA/TXDMA engine */

	if (!MP_TEST_FLAG(etdev, fMP_ADAPTER_LOWER_POWER)) {
@@ -285,7 +285,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev) 


void ConfigRxMacRegs(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *pRxMac = &etdev->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac;

	RXMAC_WOL_SA_LO_t sa_lo;

	RXMAC_WOL_SA_HI_t sa_hi;

	RXMAC_PF_CTRL_t pf_ctrl = { 0 };
@@ -427,7 +427,7 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev) 


void ConfigTxMacRegs(struct et131x_adapter *etdev)

{

	struct _TXMAC_t __iomem *pTxMac = &etdev->CSRAddress->txmac;

	struct _TXMAC_t __iomem *pTxMac = &etdev->regs->txmac;

	TXMAC_CF_PARAM_t Local;



	DBG_ENTER(et131x_dbginfo);
@@ -450,7 +450,7 @@ void ConfigTxMacRegs(struct et131x_adapter *etdev) 
void ConfigMacStatRegs(struct et131x_adapter *etdev)

{

	struct _MAC_STAT_t __iomem *pDevMacStat =

		&etdev->CSRAddress->macStat;

		&etdev->regs->macStat;



	DBG_ENTER(et131x_dbginfo);
@@ -581,7 +581,7 @@ void UpdateMacStatHostCounters(struct et131x_adapter *etdev) 
{

	struct _ce_stats_t *stats = &etdev->Stats;

	struct _MAC_STAT_t __iomem *pDevMacStat =

		&etdev->CSRAddress->macStat;

		&etdev->regs->macStat;



	stats->collisions += readl(&pDevMacStat->TNcl);

	stats->first_collision += readl(&pDevMacStat->TScl);
@@ -619,11 +619,11 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev) 
	/* Read the interrupt bits from the register(s).  These are Clear On

	 * Write.

	 */

	Carry1.value = readl(&etdev->CSRAddress->macStat.Carry1.value);

	Carry2.value = readl(&etdev->CSRAddress->macStat.Carry2.value);

	Carry1.value = readl(&etdev->regs->macStat.Carry1.value);

	Carry2.value = readl(&etdev->regs->macStat.Carry2.value);



	writel(Carry1.value, &etdev->CSRAddress->macStat.Carry1.value);

	writel(Carry2.value, &etdev->CSRAddress->macStat.Carry2.value);

	writel(Carry1.value, &etdev->regs->macStat.Carry1.value);

	writel(Carry2.value, &etdev->regs->macStat.Carry2.value);



	/* We need to do update the host copy of all the MAC_STAT counters.

	 * For each counter, check it's overflow bit.  If the overflow bit is
@@ -665,7 +665,7 @@ void HandleMacStatInterrupt(struct et131x_adapter *etdev) 


void SetupDeviceForMulticast(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;

	uint32_t nIndex;

	uint32_t result;

	uint32_t hash1 = 0;
@@ -718,7 +718,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev) 
	}



	/* Write out the new hash to the device */

	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);

	if (pm_csr.bits.pm_phy_sw_coma == 0) {

		writel(hash1, &rxmac->multi_hash1);

		writel(hash2, &rxmac->multi_hash2);
@@ -731,7 +731,7 @@ void SetupDeviceForMulticast(struct et131x_adapter *etdev) 


void SetupDeviceForUnicast(struct et131x_adapter *etdev)

{

	struct _RXMAC_t __iomem *rxmac = &etdev->CSRAddress->rxmac;

	struct _RXMAC_t __iomem *rxmac = &etdev->regs->rxmac;

	RXMAC_UNI_PF_ADDR1_t uni_pf1;

	RXMAC_UNI_PF_ADDR2_t uni_pf2;

	RXMAC_UNI_PF_ADDR3_t uni_pf3;
@@ -763,7 +763,7 @@ void SetupDeviceForUnicast(struct et131x_adapter *etdev) 
	uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];

	uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];



	pm_csr.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	pm_csr.value = readl(&etdev->regs->global.pm_csr.value);

	if (pm_csr.bits.pm_phy_sw_coma == 0) {

		writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);

		writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);

drivers/staging/et131x/et1310_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@ static int et131x_xcvr_init(struct et131x_adapter *adapter); 
int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,

	      uint8_t xcvrReg, uint16_t *value)

{

	struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;

	struct _MAC_t __iomem *mac = &adapter->regs->mac;

	int status = 0;

	uint32_t delay;

	MII_MGMT_ADDR_t miiAddr;
@@ -202,7 +202,7 @@ int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr, 
 */

int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)

{

	struct _MAC_t __iomem *mac = &adapter->CSRAddress->mac;

	struct _MAC_t __iomem *mac = &adapter->regs->mac;

	int status = 0;

	uint8_t xcvrAddr = adapter->Stats.xcvr_addr;

	uint32_t delay;

drivers/staging/et131x/et1310_pm.c

+5 −5
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ void EnablePhyComa(struct et131x_adapter *etdev) 


	DBG_ENTER(et131x_dbginfo);



	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);



	/* Save the GbE PHY speed and duplex modes. Need to restore this

	 * when cable is plugged back in
@@ -144,11 +144,11 @@ void EnablePhyComa(struct et131x_adapter *etdev) 
	GlobalPmCSR.bits.pm_sysclk_gate = 0;

	GlobalPmCSR.bits.pm_txclk_gate = 0;

	GlobalPmCSR.bits.pm_rxclk_gate = 0;

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);



	/* Program gigE PHY in to Coma mode */

	GlobalPmCSR.bits.pm_phy_sw_coma = 1;

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);



	DBG_LEAVE(et131x_dbginfo);

}
@@ -163,14 +163,14 @@ void DisablePhyComa(struct et131x_adapter *etdev) 


	DBG_ENTER(et131x_dbginfo);



	GlobalPmCSR.value = readl(&etdev->CSRAddress->global.pm_csr.value);

	GlobalPmCSR.value = readl(&etdev->regs->global.pm_csr.value);



	/* Disable phy_sw_coma register and re-enable JAGCore clocks */

	GlobalPmCSR.bits.pm_sysclk_gate = 1;

	GlobalPmCSR.bits.pm_txclk_gate = 1;

	GlobalPmCSR.bits.pm_rxclk_gate = 1;

	GlobalPmCSR.bits.pm_phy_sw_coma = 0;

	writel(GlobalPmCSR.value, &etdev->CSRAddress->global.pm_csr.value);

	writel(GlobalPmCSR.value, &etdev->regs->global.pm_csr.value);



	/* Restore the GbE PHY speed and duplex modes;

	 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY

drivers/staging/et131x/et1310_rx.c

+13 −13
Original line number Diff line number Diff line
@@ -680,7 +680,7 @@ void et131x_rfd_resources_free(struct et131x_adapter *adapter, MP_RFD *pMpRfd) 
 */

void ConfigRxDmaRegs(struct et131x_adapter *etdev)

{

	struct _RXDMA_t __iomem *pRxDma = &etdev->CSRAddress->rxdma;

	struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;

	struct _rx_ring_t *pRxLocal = &etdev->RxRing;

	PFBR_DESC_t pFbrEntry;

	uint32_t iEntry;
@@ -817,8 +817,8 @@ void SetRxDmaTimer(struct et131x_adapter *etdev) 
	 */

	if ((etdev->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) ||

	    (etdev->uiLinkSpeed == TRUEPHY_SPEED_10MBPS)) {

		writel(0, &etdev->CSRAddress->rxdma.max_pkt_time.value);

		writel(1, &etdev->CSRAddress->rxdma.num_pkt_done.value);

		writel(0, &etdev->regs->rxdma.max_pkt_time.value);

		writel(1, &etdev->regs->rxdma.num_pkt_done.value);

	}

}
@@ -833,11 +833,11 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev) 
	DBG_ENTER(et131x_dbginfo);



	/* Setup the receive dma configuration register */

	writel(0x00002001, &etdev->CSRAddress->rxdma.csr.value);

	csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);

	writel(0x00002001, &etdev->regs->rxdma.csr.value);

	csr.value = readl(&etdev->regs->rxdma.csr.value);

	if (csr.bits.halt_status != 1) {

		udelay(5);

		csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);

		csr.value = readl(&etdev->regs->rxdma.csr.value);

		if (csr.bits.halt_status != 1)

			DBG_ERROR(et131x_dbginfo,

				"RX Dma failed to enter halt state. CSR 0x%08x\n",
@@ -857,7 +857,7 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) 


	if (etdev->RegistryPhyLoopbk)

		/* RxDMA is disabled for loopback operation. */

		writel(0x1, &etdev->CSRAddress->rxdma.csr.value);

		writel(0x1, &etdev->regs->rxdma.csr.value);

	else {

	/* Setup the receive dma configuration register for normal operation */

		RXDMA_CSR_t csr = { 0 };
@@ -878,12 +878,12 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev) 
		else if (etdev->RxRing.Fbr0BufferSize == 1024)

			csr.bits.fbr0_size = 3;

#endif

		writel(csr.value, &etdev->CSRAddress->rxdma.csr.value);

		writel(csr.value, &etdev->regs->rxdma.csr.value);



		csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);

		csr.value = readl(&etdev->regs->rxdma.csr.value);

		if (csr.bits.halt_status != 0) {

			udelay(5);

			csr.value = readl(&etdev->CSRAddress->rxdma.csr.value);

			csr.value = readl(&etdev->regs->rxdma.csr.value);

			if (csr.bits.halt_status != 0) {

				DBG_ERROR(et131x_dbginfo,

					"RX Dma failed to exit halt state.  CSR 0x%08x\n",
@@ -978,7 +978,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev) 
	}



	writel(pRxLocal->local_psr_full.value,

	       &etdev->CSRAddress->rxdma.psr_full_offset.value);

	       &etdev->regs->rxdma.psr_full_offset.value);



#ifndef USE_FBR0

	if (ringIndex != 1) {
@@ -1273,7 +1273,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) 
	if ((PacketArrayCount == NUM_PACKETS_HANDLED) || TempUnfinishedRec) {

		etdev->RxRing.UnfinishedReceives = true;

		writel(etdev->RegistryTxTimeInterval * NANO_IN_A_MICRO,

		       &etdev->CSRAddress->global.watchdog_timer);

		       &etdev->regs->global.watchdog_timer);

	} else {

		/* Watchdog timer will disable itself if appropriate. */

		etdev->RxRing.UnfinishedReceives = false;
@@ -1290,7 +1290,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev) 
void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)

{

	struct _rx_ring_t *pRxLocal = &etdev->RxRing;

	struct _RXDMA_t __iomem *pRxDma = &etdev->CSRAddress->rxdma;

	struct _RXDMA_t __iomem *pRxDma = &etdev->regs->rxdma;

	uint16_t bi = pMpRfd->iBufferIndex;

	uint8_t ri = pMpRfd->iRingIndex;

	unsigned long flags;