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Commit f3e2a51f authored by Borislav Petkov's avatar Borislav Petkov Committed by Thomas Gleixner
Browse files

x86/microcode: Use native CPUID to tickle out microcode revision 



Intel supplies the microcode revision value in MSR 0x8b
(IA32_BIOS_SIGN_ID) after CPUID(1) has been executed. Execute it each
time before reading that MSR.

It used to do sync_core() which did do CPUID but

  c198b121 ("x86/asm: Rewrite sync_core() to use IRET-to-self")

changed the sync_core() implementation so we better make the microcode
loading case explicit, as the SDM documents it.

Reported-and-tested-by: default avatarJun'ichi Nomura <j-nomura@ce.jp.nec.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/20170109114147.5082-3-bp@alien8.de


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 5dedade6

arch/x86/kernel/cpu/intel.c

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) 


		wrmsr(MSR_IA32_UCODE_REV, 0, 0);

		/* Required by the SDM */

		sync_core();

		native_cpuid_eax(1);

		rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);

	}

arch/x86/kernel/cpu/microcode/intel.c

+3 −23
Original line number Diff line number Diff line
@@ -368,26 +368,6 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) 
	return patch;

}



static void cpuid_1(void)

{

	/*

	 * According to the Intel SDM, Volume 3, 9.11.7:

	 *

	 *   CPUID returns a value in a model specific register in

	 *   addition to its usual register return values. The

	 *   semantics of CPUID cause it to deposit an update ID value

	 *   in the 64-bit model-specific register at address 08BH

	 *   (IA32_BIOS_SIGN_ID). If no update is present in the

	 *   processor, the value in the MSR remains unmodified.

	 *

	 * Use native_cpuid -- this code runs very early and we don't

	 * want to mess with paravirt.

	 */

	unsigned int eax = 1, ebx, ecx = 0, edx;



	native_cpuid(&eax, &ebx, &ecx, &edx);

}



static int collect_cpu_info_early(struct ucode_cpu_info *uci)

{

	unsigned int val[2];
@@ -413,7 +393,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci) 
	native_wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	cpuid_1();

	native_cpuid_eax(1);



	/* get the current revision from MSR 0x8B */

	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -613,7 +593,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) 
	native_wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	cpuid_1();

	native_cpuid_eax(1);



	/* get the current revision from MSR 0x8B */

	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -825,7 +805,7 @@ static int apply_microcode_intel(int cpu) 
	wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	cpuid_1();

	native_cpuid_eax(1);



	/* get the current revision from MSR 0x8B */

	rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);