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Commit f3c67fdd authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915/chv: Add DPFLIPSTAT register bits for Cherryview 



CHV has pipe C and PSR which cause changes to DPFLIPSTAT.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 8cc96e7c

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -3464,12 +3464,19 @@ enum punit_power_well { 
#define   SPRITED_FLIP_DONE_INT_EN		(1<<26)

#define   SPRITEC_FLIP_DONE_INT_EN		(1<<25)

#define   PLANEB_FLIP_DONE_INT_EN		(1<<24)

#define   PIPE_PSR_INT_EN			(1<<22)

#define   PIPEA_LINE_COMPARE_INT_EN		(1<<21)

#define   PIPEA_HLINE_INT_EN			(1<<20)

#define   PIPEA_VBLANK_INT_EN			(1<<19)

#define   SPRITEB_FLIP_DONE_INT_EN		(1<<18)

#define   SPRITEA_FLIP_DONE_INT_EN		(1<<17)

#define   PLANEA_FLIPDONE_INT_EN		(1<<16)

#define   PIPEC_LINE_COMPARE_INT_EN		(1<<13)

#define   PIPEC_HLINE_INT_EN			(1<<12)

#define   PIPEC_VBLANK_INT_EN			(1<<11)

#define   SPRITEF_FLIPDONE_INT_EN		(1<<10)

#define   SPRITEE_FLIPDONE_INT_EN		(1<<9)

#define   PLANEC_FLIPDONE_INT_EN		(1<<8)



#define DPINVGTT				(VLV_DISPLAY_BASE + 0x7002c) /* VLV only */

#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)