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Commit f3ababa8 authored by Doug Anderson's avatar Doug Anderson Committed by Linus Walleij
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pinctrl: Add mux options 3 and 4 for rockchip pinctrl 



Newer Rockchip SoCs have more muxing slots.  Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.

Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 4f671cb2

Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt

+3 −3
Original line number Diff line number Diff line
@@ -2,8 +2,8 @@ 


The Rockchip Pinmux Controller, enables the IC

to share one PAD to several functional blocks. The sharing is done by

multiplexing the PAD input/output signals. For each PAD there are up to

4 muxing options with option 0 being the use as a GPIO.

multiplexing the PAD input/output signals. For each PAD there are several

muxing options with option 0 being the use as a GPIO.



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes: 
Required properties for pin configuration node:

  - rockchip,pins: 3 integers array, represents a group of pins mux and config

    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.

    The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.

    The MUX 0 means gpio and MUX 1 to N mean the specific device function.

    The phandle of a node containing the generic pinconfig options

    to use, as described in pinctrl-bindings.txt in this directory.

include/dt-bindings/pinctrl/rockchip.h

+2 −0
Original line number Diff line number Diff line
@@ -28,5 +28,7 @@ 
#define RK_FUNC_GPIO	0

#define RK_FUNC_1	1

#define RK_FUNC_2	2

#define RK_FUNC_3	3

#define RK_FUNC_4	4



#endif