Merge branch 'qed-next' (f3a6f592) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/net/ethernet/qlogic/qed/qed.h

+17 −2

Original line number	Diff line number	Diff line
		@@ -154,7 +154,10 @@ struct qed_qm_iids {
		u32 tids;
		};

		enum QED_RESOURCES {
		/* HW / FW resources, output of features supported below, most information
		* is received from MFW.
		*/
		enum qed_resources {
		QED_SB,
		QED_L2_QUEUE,
		QED_VPORT,
		@@ -166,6 +169,7 @@ enum QED_RESOURCES {
		QED_RDMA_CNQ_RAM,
		QED_ILT,
		QED_LL2_QUEUE,
		QED_CMDQS_CQS,
		QED_RDMA_STATS_QUEUE,
		QED_MAX_RESC,
		};
		@@ -174,6 +178,7 @@ enum QED_FEATURE {
		QED_PF_L2_QUE,
		QED_VF,
		QED_RDMA_CNQ,
		QED_VF_L2_QUE,
		QED_MAX_FEATURES,
		};

		@@ -195,6 +200,11 @@ enum qed_dev_cap {
		QED_DEV_CAP_ROCE,
		};

		enum qed_wol_support {
		QED_WOL_SUPPORT_NONE,
		QED_WOL_SUPPORT_PME,
		};

		struct qed_hw_info {
		/* PCI personality */
		enum qed_pci_personality personality;
		@@ -226,6 +236,9 @@ struct qed_hw_info {
		u32 port_mode;
		u32 hw_mode;
		unsigned long device_capabilities;
		u16 mtu;

		enum qed_wol_support b_wol_support;
		};

		struct qed_hw_cid_data {
		@@ -538,7 +551,9 @@ struct qed_dev {
		u8 mcp_rev;
		u8 boot_mode;

		u8 wol;
		/* WoL related configurations */
		u8 wol_config;
		u8 wol_mac[ETH_ALEN];

		u32 int_mode;
		enum qed_coalescing_mode int_coalescing_mode;

drivers/net/ethernet/qlogic/qed/qed_dev.c

+314 −68

Original line number	Diff line number	Diff line
		@@ -1057,8 +1057,10 @@ int qed_hw_init(struct qed_dev *cdev,
		bool allow_npar_tx_switch,
		const u8 *bin_fw_data)
		{
		u32 load_code, param;
		int rc, mfw_rc, i;
		u32 load_code, param, drv_mb_param;
		bool b_default_mtu = true;
		struct qed_hwfn *p_hwfn;
		int rc = 0, mfw_rc, i;

		if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
		DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
		@@ -1074,6 +1076,12 @@ int qed_hw_init(struct qed_dev *cdev,
		for_each_hwfn(cdev, i) {
		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];

		/* If management didn't provide a default, set one of our own */
		if (!p_hwfn->hw_info.mtu) {
		p_hwfn->hw_info.mtu = 1500;
		b_default_mtu = false;
		}

		if (IS_VF(cdev)) {
		p_hwfn->b_int_enabled = 1;
		continue;
		@@ -1157,6 +1165,38 @@ int qed_hw_init(struct qed_dev *cdev,
		p_hwfn->hw_init_done = true;
		}

		if (IS_PF(cdev)) {
		p_hwfn = QED_LEADING_HWFN(cdev);
		drv_mb_param = (FW_MAJOR_VERSION << 24) \|
		(FW_MINOR_VERSION << 16) \|
		(FW_REVISION_VERSION << 8) \|
		(FW_ENGINEERING_VERSION);
		rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
		DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
		drv_mb_param, &load_code, &param);
		if (rc)
		DP_INFO(p_hwfn, "Failed to update firmware version\n");

		if (!b_default_mtu) {
		rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
		p_hwfn->hw_info.mtu);
		if (rc)
		DP_INFO(p_hwfn,
		"Failed to update default mtu\n");
		}

		rc = qed_mcp_ov_update_driver_state(p_hwfn,
		p_hwfn->p_main_ptt,
		QED_OV_DRIVER_STATE_DISABLED);
		if (rc)
		DP_INFO(p_hwfn, "Failed to update driver state\n");

		rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
		QED_OV_ESWITCH_VEB);
		if (rc)
		DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
		}

		return 0;
		}

		@@ -1324,8 +1364,24 @@ int qed_hw_reset(struct qed_dev *cdev)
		{
		int rc = 0;
		u32 unload_resp, unload_param;
		u32 wol_param;
		int i;

		switch (cdev->wol_config) {
		case QED_OV_WOL_DISABLED:
		wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
		break;
		case QED_OV_WOL_ENABLED:
		wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
		break;
		default:
		DP_NOTICE(cdev,
		"Unknown WoL configuration %02x\n", cdev->wol_config);
		/* Fallthrough */
		case QED_OV_WOL_DEFAULT:
		wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
		}

		for_each_hwfn(cdev, i) {
		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];

		@@ -1354,8 +1410,7 @@ int qed_hw_reset(struct qed_dev *cdev)

		/* Send unload command to MCP */
		rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
		DRV_MSG_CODE_UNLOAD_REQ,
		DRV_MB_PARAM_UNLOAD_WOL_MCP,
		DRV_MSG_CODE_UNLOAD_REQ, wol_param,
		&unload_resp, &unload_param);
		if (rc) {
		DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n");
		@@ -1421,6 +1476,7 @@ static void get_function_id(struct qed_hwfn *p_hwfn)
		static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
		{
		u32 *feat_num = p_hwfn->hw_info.feat_num;
		struct qed_sb_cnt_info sb_cnt_info;
		int num_features = 1;

		if (IS_ENABLED(CONFIG_QED_RDMA) &&
		@@ -1439,53 +1495,257 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
		feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
		num_features,
		RESC_NUM(p_hwfn, QED_L2_QUEUE));
		DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
		"#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
		feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
		num_features);

		memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
		qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
		feat_num[QED_VF_L2_QUE] =
		min_t(u32,
		RESC_NUM(p_hwfn, QED_L2_QUEUE) -
		FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt);

		DP_VERBOSE(p_hwfn,
		NETIF_MSG_PROBE,
		"#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n",
		(int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
		(int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
		(int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
		RESC_NUM(p_hwfn, QED_SB), num_features);
		}

		static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
		static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id)
		{
		enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;

		switch (res_id) {
		case QED_SB:
		mfw_res_id = RESOURCE_NUM_SB_E;
		break;
		case QED_L2_QUEUE:
		mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
		break;
		case QED_VPORT:
		mfw_res_id = RESOURCE_NUM_VPORT_E;
		break;
		case QED_RSS_ENG:
		mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
		break;
		case QED_PQ:
		mfw_res_id = RESOURCE_NUM_PQ_E;
		break;
		case QED_RL:
		mfw_res_id = RESOURCE_NUM_RL_E;
		break;
		case QED_MAC:
		case QED_VLAN:
		/* Each VFC resource can accommodate both a MAC and a VLAN */
		mfw_res_id = RESOURCE_VFC_FILTER_E;
		break;
		case QED_ILT:
		mfw_res_id = RESOURCE_ILT_E;
		break;
		case QED_LL2_QUEUE:
		mfw_res_id = RESOURCE_LL2_QUEUE_E;
		break;
		case QED_RDMA_CNQ_RAM:
		case QED_CMDQS_CQS:
		/* CNQ/CMDQS are the same resource */
		mfw_res_id = RESOURCE_CQS_E;
		break;
		case QED_RDMA_STATS_QUEUE:
		mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
		break;
		default:
		break;
		}

		return mfw_res_id;
		}

		static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn,
		enum qed_resources res_id)
		{
		u8 enabled_func_idx = p_hwfn->enabled_func_idx;
		u32 *resc_start = p_hwfn->hw_info.resc_start;
		u8 num_funcs = p_hwfn->num_funcs_on_engine;
		u32 *resc_num = p_hwfn->hw_info.resc_num;
		struct qed_sb_cnt_info sb_cnt_info;
		int i, max_vf_vlan_filters;
		u32 dflt_resc_num = 0;

		switch (res_id) {
		case QED_SB:
		memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));
		qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
		dflt_resc_num = sb_cnt_info.sb_cnt;
		break;
		case QED_L2_QUEUE:
		dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs;
		break;
		case QED_VPORT:
		dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs;
		break;
		case QED_RSS_ENG:
		dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs;
		break;
		case QED_PQ:
		/* The granularity of the PQs is 8 */
		dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs;
		dflt_resc_num &= ~0x7;
		break;
		case QED_RL:
		dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
		break;
		case QED_MAC:
		case QED_VLAN:
		/* Each VFC resource can accommodate both a MAC and a VLAN */
		dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
		break;
		case QED_ILT:
		dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs;
		break;
		case QED_LL2_QUEUE:
		dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
		break;
		case QED_RDMA_CNQ_RAM:
		case QED_CMDQS_CQS:
		/* CNQ/CMDQS are the same resource */
		dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs;
		break;
		case QED_RDMA_STATS_QUEUE:
		dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs;
		break;
		default:
		break;
		}

		#ifdef CONFIG_QED_SRIOV
		max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS;
		#else
		max_vf_vlan_filters = 0;
		#endif
		return dflt_resc_num;
		}

		static const char *qed_hw_get_resc_name(enum qed_resources res_id)
		{
		switch (res_id) {
		case QED_SB:
		return "SB";
		case QED_L2_QUEUE:
		return "L2_QUEUE";
		case QED_VPORT:
		return "VPORT";
		case QED_RSS_ENG:
		return "RSS_ENG";
		case QED_PQ:
		return "PQ";
		case QED_RL:
		return "RL";
		case QED_MAC:
		return "MAC";
		case QED_VLAN:
		return "VLAN";
		case QED_RDMA_CNQ_RAM:
		return "RDMA_CNQ_RAM";
		case QED_ILT:
		return "ILT";
		case QED_LL2_QUEUE:
		return "LL2_QUEUE";
		case QED_CMDQS_CQS:
		return "CMDQS_CQS";
		case QED_RDMA_STATS_QUEUE:
		return "RDMA_STATS_QUEUE";
		default:
		return "UNKNOWN_RESOURCE";
		}
		}

		qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
		static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
		enum qed_resources res_id)
		{
		u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param;
		u32 p_resc_num, p_resc_start;
		struct resource_info resc_info;
		int rc;

		resc_num[QED_SB] = min_t(u32,
		(MAX_SB_PER_PATH_BB / num_funcs),
		sb_cnt_info.sb_cnt);
		resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
		resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
		resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
		resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
		resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]);
		resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
		resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /For vlan0/) /
		num_funcs;
		resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs;
		resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs;
		resc_num[QED_RDMA_CNQ_RAM] = NUM_OF_CMDQS_CQS / num_funcs;
		resc_num[QED_RDMA_STATS_QUEUE] = RDMA_NUM_STATISTIC_COUNTERS_BB /
		num_funcs;

		for (i = 0; i < QED_MAX_RESC; i++)
		resc_start[i] = resc_num[i] * enabled_func_idx;
		p_resc_num = &RESC_NUM(p_hwfn, res_id);
		p_resc_start = &RESC_START(p_hwfn, res_id);

		/* Default values assumes that each function received equal share */
		dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id);
		if (!dflt_resc_num) {
		DP_ERR(p_hwfn,
		"Failed to get default amount for resource %d [%s]\n",
		res_id, qed_hw_get_resc_name(res_id));
		return -EINVAL;
		}
		dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx;

		memset(&resc_info, 0, sizeof(resc_info));
		resc_info.res_id = qed_hw_get_mfw_res_id(res_id);
		if (resc_info.res_id == RESOURCE_NUM_INVALID) {
		DP_ERR(p_hwfn,
		"Failed to match resource %d [%s] with the MFW resources\n",
		res_id, qed_hw_get_resc_name(res_id));
		return -EINVAL;
		}

		rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info,
		&mcp_resp, &mcp_param);
		if (rc) {
		DP_NOTICE(p_hwfn,
		"MFW response failure for an allocation request for resource %d [%s]\n",
		res_id, qed_hw_get_resc_name(res_id));
		return rc;
		}

		/* Default driver values are applied in the following cases:
		* - The resource allocation MB command is not supported by the MFW
		* - There is an internal error in the MFW while processing the request
		* - The resource ID is unknown to the MFW
		*/
		if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK &&
		mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) {
		DP_NOTICE(p_hwfn,
		"Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n",
		res_id,
		qed_hw_get_resc_name(res_id),
		mcp_resp, dflt_resc_num, dflt_resc_start);
		*p_resc_num = dflt_resc_num;
		*p_resc_start = dflt_resc_start;
		goto out;
		}

		/* Special handling for status blocks; Would be revised in future */
		if (res_id == QED_SB) {
		resc_info.size -= 1;
		resc_info.offset -= p_hwfn->enabled_func_idx;
		}

		*p_resc_num = resc_info.size;
		*p_resc_start = resc_info.offset;

		out:
		/* PQs have to divide by 8 [that's the HW granularity].
		* Reduce number so it would fit.
		*/
		if ((res_id == QED_PQ) && ((p_resc_num % 8) \|\| (p_resc_start % 8))) {
		DP_INFO(p_hwfn,
		"PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
		*p_resc_num,
		(*p_resc_num) & ~0x7,
		p_resc_start, (p_resc_start) & ~0x7);
		*p_resc_num &= ~0x7;
		*p_resc_start &= ~0x7;
		}

		return 0;
		}

		static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
		{
		u8 res_id;
		int rc;

		for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
		rc = qed_hw_set_resc_info(p_hwfn, res_id);
		if (rc)
		return rc;
		}

		/* Sanity for ILT */
		if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) {
		if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) {
		DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
		RESC_START(p_hwfn, QED_ILT),
		RESC_END(p_hwfn, QED_ILT) - 1);
		@@ -1495,34 +1755,12 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn)
		qed_hw_set_feat(p_hwfn);

		DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
		"The numbers for each resource are:\n"
		"SB = %d start = %d\n"
		"L2_QUEUE = %d start = %d\n"
		"VPORT = %d start = %d\n"
		"PQ = %d start = %d\n"
		"RL = %d start = %d\n"
		"MAC = %d start = %d\n"
		"VLAN = %d start = %d\n"
		"ILT = %d start = %d\n"
		"LL2_QUEUE = %d start = %d\n",
		p_hwfn->hw_info.resc_num[QED_SB],
		p_hwfn->hw_info.resc_start[QED_SB],
		p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
		p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
		p_hwfn->hw_info.resc_num[QED_VPORT],
		p_hwfn->hw_info.resc_start[QED_VPORT],
		p_hwfn->hw_info.resc_num[QED_PQ],
		p_hwfn->hw_info.resc_start[QED_PQ],
		p_hwfn->hw_info.resc_num[QED_RL],
		p_hwfn->hw_info.resc_start[QED_RL],
		p_hwfn->hw_info.resc_num[QED_MAC],
		p_hwfn->hw_info.resc_start[QED_MAC],
		p_hwfn->hw_info.resc_num[QED_VLAN],
		p_hwfn->hw_info.resc_start[QED_VLAN],
		p_hwfn->hw_info.resc_num[QED_ILT],
		p_hwfn->hw_info.resc_start[QED_ILT],
		RESC_NUM(p_hwfn, QED_LL2_QUEUE),
		RESC_START(p_hwfn, QED_LL2_QUEUE));
		"The numbers for each resource are:\n");
		for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
		DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
		qed_hw_get_resc_name(res_id),
		RESC_NUM(p_hwfn, res_id),
		RESC_START(p_hwfn, res_id));

		return 0;
		}
		@@ -1801,6 +2039,9 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,

		qed_get_num_funcs(p_hwfn, p_ptt);

		if (qed_mcp_is_init(p_hwfn))
		p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;

		return qed_hw_get_resc(p_hwfn);
		}

		@@ -1975,8 +2216,13 @@ int qed_hw_prepare(struct qed_dev *cdev,

		void qed_hw_remove(struct qed_dev *cdev)
		{
		struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
		int i;

		if (IS_PF(cdev))
		qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
		QED_OV_DRIVER_STATE_NOT_LOADED);

		for_each_hwfn(cdev, i) {
		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+119 −1

Original line number	Diff line number	Diff line
		@@ -8529,6 +8529,41 @@ struct mdump_config_stc {
		u32 valid_logs;
		};

		enum resource_id_enum {
		RESOURCE_NUM_SB_E = 0,
		RESOURCE_NUM_L2_QUEUE_E = 1,
		RESOURCE_NUM_VPORT_E = 2,
		RESOURCE_NUM_VMQ_E = 3,
		RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
		RESOURCE_FACTOR_RSS_PER_VF_E = 5,
		RESOURCE_NUM_RL_E = 6,
		RESOURCE_NUM_PQ_E = 7,
		RESOURCE_NUM_VF_E = 8,
		RESOURCE_VFC_FILTER_E = 9,
		RESOURCE_ILT_E = 10,
		RESOURCE_CQS_E = 11,
		RESOURCE_GFT_PROFILES_E = 12,
		RESOURCE_NUM_TC_E = 13,
		RESOURCE_NUM_RSS_ENGINES_E = 14,
		RESOURCE_LL2_QUEUE_E = 15,
		RESOURCE_RDMA_STATS_QUEUE_E = 16,
		RESOURCE_MAX_NUM,
		RESOURCE_NUM_INVALID = 0xFFFFFFFF
		};

		/* Resource ID is to be filled by the driver in the MB request
		* Size, offset & flags to be filled by the MFW in the MB response
		*/
		struct resource_info {
		enum resource_id_enum res_id;
		u32 size; /* number of allocated resources */
		u32 offset; /* Offset of the 1st resource */
		u32 vf_size;
		u32 vf_offset;
		u32 flags;
		#define RESOURCE_ELEMENT_STRICT (1 << 0)
		};

		union drv_union_data {
		u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
		struct mcp_mac wol_mac;
		@@ -8549,6 +8584,7 @@ union drv_union_data {
		u64 reserved_stats[11];
		struct ocbb_data_stc ocbb_info;
		struct temperature_status_stc temp_info;
		struct resource_info resource;
		struct bist_nvm_image_att nvm_image_att;
		struct mdump_config_stc mdump_config;
		};
		@@ -8564,9 +8600,19 @@ struct public_drv_mb {
		#define DRV_MSG_CODE_INIT_PHY 0x22000000
		#define DRV_MSG_CODE_LINK_RESET 0x23000000
		#define DRV_MSG_CODE_SET_DCBX 0x25000000
		#define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
		#define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
		#define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
		#define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
		#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
		#define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
		#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
		#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000

		#define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
		#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
		#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
		#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
		#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
		#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
		@@ -8574,6 +8620,13 @@ struct public_drv_mb {
		#define DRV_MSG_CODE_MCP_RESET 0x00090000
		#define DRV_MSG_CODE_SET_VERSION 0x000f0000
		#define DRV_MSG_CODE_MCP_HALT 0x00100000
		#define DRV_MSG_CODE_SET_VMAC 0x00110000
		#define DRV_MSG_CODE_GET_VMAC 0x00120000
		#define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
		#define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
		#define DRV_MSG_CODE_VMAC_TYPE_MAC 1
		#define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
		#define DRV_MSG_CODE_VMAC_TYPE_WWPN 3

		#define DRV_MSG_CODE_GET_STATS 0x00130000
		#define DRV_MSG_CODE_STATS_TYPE_LAN 1
		@@ -8585,11 +8638,16 @@ struct public_drv_mb {

		#define DRV_MSG_CODE_BIST_TEST 0x001e0000
		#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
		#define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
		#define DRV_MSG_CODE_OS_WOL 0x002e0000

		#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff

		u32 drv_mb_param;
		#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
		#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
		#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
		#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
		#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
		#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3

		@@ -8602,13 +8660,59 @@ struct public_drv_mb {
		#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
		#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0

		#define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
		#define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
		#define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
		#define DRV_MB_PARAM_OV_CURR_CFG_OS 1
		#define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
		#define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3

		#define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
		#define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
		#define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
		#define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
		#define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
		#define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF

		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
		#define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5

		#define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
		#define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF

		#define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT \| \
		DRV_MB_PARAM_WOL_DISABLED \| \
		DRV_MB_PARAM_WOL_ENABLED)
		#define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
		#define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
		#define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED

		#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE \| \
		DRV_MB_PARAM_ESWITCH_MODE_VEB \| \
		DRV_MB_PARAM_ESWITCH_MODE_VEPA)
		#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
		#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
		#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2

		#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
		#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
		#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2

		/* Resource Allocation params - Driver version support */
		#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
		#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
		#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
		#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0

		#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
		#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
		#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
		#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4

		#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
		#define DRV_MB_PARAM_BIST_RC_PASSED 1
		@@ -8617,6 +8721,8 @@ struct public_drv_mb {

		#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
		#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
		#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
		#define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00

		u32 fw_mb_header;
		#define FW_MSG_CODE_MASK 0xffff0000
		@@ -8631,15 +8737,27 @@ struct public_drv_mb {
		#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
		#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
		#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
		#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
		#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
		#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
		#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000

		#define FW_MSG_CODE_NVM_OK 0x00010000
		#define FW_MSG_CODE_OK 0x00160000

		#define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
		#define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000

		#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff

		u32 fw_mb_param;

		/* get pf rdma protocol command responce */
		#define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
		#define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
		#define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
		#define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3

		u32 drv_pulse_mb;
		#define DRV_PULSE_SEQ_MASK 0x00007fff
		#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000

drivers/net/ethernet/qlogic/qed/qed_int.c

+31 −1

Original line number	Diff line number	Diff line
		@@ -3030,6 +3030,31 @@ int qed_int_igu_read_cam(struct qed_hwfn p_hwfn, struct qed_ptt p_ptt)
		}
		}
		}

		/* There's a possibility the igu_sb_cnt_iov doesn't properly reflect
		* the number of VF SBs [especially for first VF on engine, as we can't
		* diffrentiate between empty entries and its entries].
		* Since we don't really support more SBs than VFs today, prevent any
		* such configuration by sanitizing the number of SBs to equal the
		* number of VFs.
		*/
		if (IS_PF_SRIOV(p_hwfn)) {
		u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs;

		if (total_vfs < p_igu_info->free_blks) {
		DP_VERBOSE(p_hwfn,
		(NETIF_MSG_INTR \| QED_MSG_IOV),
		"Limiting number of SBs for IOV - %04x --> %04x\n",
		p_igu_info->free_blks,
		p_hwfn->cdev->p_iov_info->total_vfs);
		p_igu_info->free_blks = total_vfs;
		} else if (total_vfs > p_igu_info->free_blks) {
		DP_NOTICE(p_hwfn,
		"IGU has only %04x SBs for VFs while the device has %04x VFs\n",
		p_igu_info->free_blks, total_vfs);
		return -EINVAL;
		}
		}
		p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks;

		DP_VERBOSE(
		@@ -3163,7 +3188,12 @@ u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
		return sb_id - p_info->igu_base_sb;
		} else if ((sb_id >= p_info->igu_base_sb_iov) &&
		(sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
		return sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt;
		/* We want the first VF queue to be adjacent to the
		* last PF queue. Since L2 queues can be partial to
		* SBs, we'll use the feature instead.
		*/
		return sb_id - p_info->igu_base_sb_iov +
		FEAT_NUM(p_hwfn, QED_PF_L2_QUE);
		} else {
		DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id);
		return 0;

drivers/net/ethernet/qlogic/qed/qed_l2.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1691,7 +1691,7 @@ static int qed_fill_eth_dev_info(struct qed_dev *cdev,
		}

		qed_vf_get_num_vlan_filters(&cdev->hwfns[0],
		&info->num_vlan_filters);
		(u8 *)&info->num_vlan_filters);
		qed_vf_get_port_mac(&cdev->hwfns[0], info->port_mac);

		info->is_legacy = !!cdev->hwfns[0].vf_iov_info->b_pre_fp_hsi;