Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f36c4720 authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: Add support for the M5150 processor 



The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5  in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4975b86a

arch/mips/include/asm/cpu-type.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ static inline int __pure __get_cpu_type(const int cpu_type) 
	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

	case CPU_P5600:

	case CPU_M5150:

#endif



#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1

arch/mips/include/asm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ enum cpu_type_enum { 
	CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,

	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,

	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,

	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,



	/*

	 * MIPS64 class processors

arch/mips/kernel/idle.c

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ void __init check_wait(void) 
	case CPU_INTERAPTIV:

	case CPU_PROAPTIV:

	case CPU_P5600:

	case CPU_M5150:

		cpu_wait = r4k_wait;

		if (read_c0_config7() & MIPS_CONF7_WII)

			cpu_wait = r4k_wait_irqoff;

arch/mips/mm/c-r4k.c

+1 −0
Original line number Diff line number Diff line
@@ -1173,6 +1173,7 @@ static void probe_pcache(void) 
	case CPU_INTERAPTIV:

	case CPU_P5600:

	case CPU_PROAPTIV:

	case CPU_M5150:

		if ((c->cputype == CPU_74K) || (c->cputype == CPU_1074K))

			alias_74k_erratum(c);

		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&

arch/mips/mm/tlbex.c

+1 −0
Original line number Diff line number Diff line
@@ -512,6 +512,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, 
		case CPU_1074K:

		case CPU_PROAPTIV:

		case CPU_P5600:

		case CPU_M5150:

			break;



		default: