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Commit f35c11b0 authored by Amit Kucheria's avatar Amit Kucheria Committed by Andy Gross
Browse files

arm64: dts: msm8996: thermal: Initialise via DT and add second controller 



We also split up the regmap address space into two, for the TM and SROT
registers. This was required to deal with different address offsets for the
TM and SROT registers across different SoC families.

8996 has two TSENS IP blocks, initialise the second one too.

Since tsens-common.c/init_common() currently only registers one address
space, the order is important (TM before SROT). This is OK since the code
doesn't really use the SROT functionality yet.

Signed-off-by: default avatarAmit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 7a0d5009

arch/arm64/boot/dts/qcom/msm8996.dtsi

+16 −6
Original line number Original line Diff line number Diff line
@@ -377,6 +377,22 @@ 
			reg = <0x740000 0x20000>;

			reg = <0x740000 0x20000>;

		};

		};





		tsens0: thermal-sensor@4a9000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4a9000 0x1000>, /* TM */

			      <0x4a8000 0x1000>; /* SROT */

			#qcom,sensors = <13>;

			#thermal-sensor-cells = <1>;

		};



		tsens1: thermal-sensor@4ad000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4ad000 0x1000>, /* TM */

			      <0x4ac000 0x1000>; /* SROT */

			#qcom,sensors = <8>;

			#thermal-sensor-cells = <1>;

		};



		tcsr: syscon@7a0000 {

		tcsr: syscon@7a0000 {

			compatible = "qcom,tcsr-msm8996", "syscon";

			compatible = "qcom,tcsr-msm8996", "syscon";

			reg = <0x7a0000 0x18000>;

			reg = <0x7a0000 0x18000>;
@@ -459,12 +475,6 @@ 
			status = "disabled";

			status = "disabled";

		};

		};





		tsens0: thermal-sensor@4a8000 {

			compatible = "qcom,msm8996-tsens";

			reg = <0x4a8000 0x2000>;

			#thermal-sensor-cells = <1>;

		};



		blsp2_uart1: serial@75b0000 {

		blsp2_uart1: serial@75b0000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x75b0000 0x1000>;

			reg = <0x75b0000 0x1000>;