Merge tag 'for-linus' of git://github.com/openrisc/linux

Open Multi-Processor Interrupt Controller

Required properties:

- compatible : This should be "openrisc,ompic"

- reg : Specifies base physical address and size of the register space. The

  size is based on the number of cores the controller has been configured

  to handle, this should be set to 8 bytes per cpu core.

- interrupt-controller : Identifies the node as an interrupt controller.

- #interrupt-cells : This should be set to 0 as this will not be an irq

  parent.

- interrupts : Specifies the interrupt line to which the ompic is wired.

Example:

ompic: interrupt-controller@98000000 {

	compatible = "openrisc,ompic";

	reg = <0x98000000 16>;

	interrupt-controller;

	#interrupt-cells = <0>;

	interrupts = <1>;

};

OpenRISC Generic SoC

====================

Boards and FPGA SoC's which support the OpenRISC standard platform.  The

platform essentially follows the conventions of the OpenRISC architecture

specification, however some aspects, such as the boot protocol have been defined

by the Linux port.

Required properties

-------------------

 - compatible: Must include "opencores,or1ksim"

CPU nodes:

----------

A "cpus" node is required.  Required properties:

 - #address-cells: Must be 1.

 - #size-cells: Must be 0.

A CPU sub-node is also required for at least CPU 0.  Since the topology may

be probed via CPS, it is not necessary to specify secondary CPUs.  Required

properties:

 - compatible: Must be "opencores,or1200-rtlsvn481".

 - reg: CPU number.

 - clock-frequency: The CPU clock frequency in Hz.

Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu@0 {

			compatible = "opencores,or1200-rtlsvn481";

			reg = <0>;

			clock-frequency = <20000000>;

		};

	};

Boot protocol

-------------

The bootloader may pass the following arguments to the kernel:

 - r3:  address of a flattened device-tree blob or 0x0.

onnn	ON Semiconductor Corp.

ontat	On Tat Industrial Company

opencores	OpenCores.org

openrisc	OpenRISC.io

option	Option NV

ORCL	Oracle Corporation

ortustech	Ortus Technology Co., Ltd.

For information about OpenRISC processors and ongoing development:

	website		http://openrisc.io

For more information about Linux on OpenRISC, please contact South Pole AB.

	email:		info@southpole.se

	website:	http://southpole.se

			http://southpoleconsulting.com

	email		openrisc@lists.librecores.org

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toolchain and, perhaps, the architectural simulator.  Steps to get these bits

in place are outlined here.

1)  The toolchain can be obtained from openrisc.io.  Instructions for building

a toolchain can be found at:

1) Toolchain

Toolchain binaries can be obtained from openrisc.io or our github releases page.

Instructions for building the different toolchains can be found on openrisc.io

or Stafford's toolchain build and release scripts.

	binaries	https://github.com/openrisc/or1k-gcc/releases

	toolchains	https://openrisc.io/software

	building	https://github.com/stffrdhrn/or1k-toolchain-build

https://github.com/openrisc/tutorials

2) Building

2) or1ksim (optional)

Build the Linux kernel as usual

or1ksim is the architectural simulator which will allow you to actually run

your OpenRISC Linux kernel if you don't have an OpenRISC processor at hand.

	make ARCH=openrisc defconfig

	make ARCH=openrisc

	git clone https://github.com/openrisc/or1ksim.git

3) Running on FPGA (optional)

	cd or1ksim

	./configure --prefix=$OPENRISC_PREFIX

	make

	make install

The OpenRISC community typically uses FuseSoC to manage building and programming

an SoC into an FPGA.  The below is an example of programming a De0 Nano

development board with the OpenRISC SoC.  During the build FPGA RTL is code

downloaded from the FuseSoC IP cores repository and built using the FPGA vendor

tools.  Binaries are loaded onto the board with openocd.

3)  Linux kernel

	git clone https://github.com/olofk/fusesoc

	cd fusesoc

	sudo pip install -e .

Build the kernel as usual

	fusesoc init

	fusesoc build de0_nano

	fusesoc pgm de0_nano

	make ARCH=openrisc defconfig

	make ARCH=openrisc

	openocd -f interface/altera-usb-blaster.cfg \

		-f board/or1k_generic.cfg

	telnet localhost 4444

	> init

	> halt; load_image vmlinux ; reset

4)  Run in architectural simulator

4) Running on a Simulator (optional)

Grab the or1ksim platform configuration file (from the or1ksim source) and

together with your freshly built vmlinux, run your kernel with the following

incantation:

QEMU is a processor emulator which we recommend for simulating the OpenRISC

platform.  Please follow the OpenRISC instructions on the QEMU website to get

Linux running on QEMU.  You can build QEMU yourself, but your Linux distribution

likely provides binary packages to support OpenRISC.

	sim -f arch/openrisc/or1ksim.cfg vmlinux

	qemu openrisc	https://wiki.qemu.org/Documentation/Platforms/OpenRISC

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