Blackfin: fix detection of cached L2 SRAM



Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly
else memory easily goes unflushed when working with DMA.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

parent c8f36dc3

arch/blackfin/include/asm/cacheflush.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -108,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr)
		addr >= _ramend && addr < physical_mem_end)
		return 1;

		#ifndef CONFIG_BFIN_L2_NOT_CACHED
		if (addr >= L2_START && addr < L2_START + L2_LENGTH)
		return 1;
		#endif

		return 0;
		}