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Commit f2d2fe95 authored by Sagar Arun Kamble's avatar Sagar Arun Kamble Committed by Daniel Vetter
Browse files

drm/i915: WaRsDisableCoarsePowerGating 



WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.

v2: Added GT3/GT4 Check.

Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarAlex Dai <yu.dai@intel.com>
[danvet: Align continuation properly.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7a58bad0

drivers/gpu/drm/i915/intel_pm.c

+7 −4
Original line number Diff line number Diff line
@@ -4877,11 +4877,14 @@ static void gen9_enable_rc6(struct drm_device *dev) 


	/*

	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.

	 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.

	 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.

	 */

	if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||

	    ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))

		I915_WRITE(GEN9_PG_ENABLE, 0);

	else

		I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?

			GEN9_MEDIA_PG_ENABLE : 0);



				(GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);