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Commit f2080b9a authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
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powerpc/perf: Add Power8 mem_access event to sysfs 



Patch add "mem_access" event to sysfs. This as-is not a raw event
supported by Power8 pmu. Instead, it is formed based on
raw event encoding specificed in isa207-common.h.

Primary PMU event used here is PM_MRK_INST_CMPL.
This event tracks only the completed marked instructions.

Random sampling mode (MMCRA[SM]) with Random Instruction
Sampling (RIS) is enabled to mark type of instructions.

With Random sampling in RLS mode with PM_MRK_INST_CMPL event,
the LDST /DATA_SRC fields in SIER identifies the memory
hierarchy level (eg: L1, L2 etc) statisfied a data-cache
miss for a marked instruction.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent d148c94c

arch/powerpc/perf/power8-events-list.h

+6 −0
Original line number Diff line number Diff line
@@ -89,3 +89,9 @@ EVENT(PM_MRK_FILT_MATCH, 0x2013c) 
EVENT(PM_MRK_FILT_MATCH_ALT,			0x3012e)

/* Alternate event code for PM_LD_MISS_L1 */

EVENT(PM_LD_MISS_L1_ALT,			0x400f0)

/*

 * Memory Access Event -- mem_access

 * Primary PMU event used here is PM_MRK_INST_CMPL, along with

 * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).

 */

EVENT(MEM_ACCESS,				0x10401e0)

arch/powerpc/perf/power8-pmu.c

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN); 
GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);

GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);

GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1);

GENERIC_EVENT_ATTR(mem_access,			MEM_ACCESS);



CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);

CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
@@ -120,6 +121,7 @@ static struct attribute *power8_events_attr[] = { 
	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),

	GENERIC_EVENT_PTR(PM_LD_REF_L1),

	GENERIC_EVENT_PTR(PM_LD_MISS_L1),

	GENERIC_EVENT_PTR(MEM_ACCESS),



	CACHE_EVENT_PTR(PM_LD_MISS_L1),

	CACHE_EVENT_PTR(PM_LD_REF_L1),