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Commit f1fe5252 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Fix FIXUP_ENDIAN non-maskable interrupt reentrancy 



FIXUP_ENDIAN uses SRR[01] with MSR_RI=1, which gets corrupted if there
is an interleaving system reset or machine check interrupt.

Set MSR_RI=0 before setting SRRs. The rfid will restore MSR.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 5ed02dbb

arch/powerpc/boot/ppc_asm.h

+7 −5
Original line number Diff line number Diff line
@@ -68,12 +68,14 @@ 


#define FIXUP_ENDIAN						   \

	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \

	b     $+36;	  /* Skip trampoline if endian is good	*/ \

	.long 0x05009f42; /* bcl 20,31,$+4			*/ \

	.long 0xa602487d; /* mflr r10				*/ \

	.long 0x1c004a39; /* addi r10,r10,28			*/ \

	b     $+44;	  /* Skip trampoline if endian is good	*/ \

	.long 0xa600607d; /* mfmsr r11				*/ \

	.long 0x01006b69; /* xori r11,r11,1			*/ \

	.long 0x00004039; /* li r10,0				*/ \

	.long 0x6401417d; /* mtmsrd r10,1			*/ \

	.long 0x05009f42; /* bcl 20,31,$+4			*/ \

	.long 0xa602487d; /* mflr r10				*/ \

	.long 0x14004a39; /* addi r10,r10,20			*/ \

	.long 0xa6035a7d; /* mtsrr0 r10				*/ \

	.long 0xa6037b7d; /* mtsrr1 r11				*/ \

	.long 0x2400004c  /* rfid				*/

arch/powerpc/include/asm/ppc_asm.h

+7 −4
Original line number Diff line number Diff line
@@ -770,15 +770,18 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) 
#else

#define FIXUP_ENDIAN						   \

	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \

	b     $+36;	  /* Skip trampoline if endian is good	*/ \

	.long 0x05009f42; /* bcl 20,31,$+4			*/ \

	.long 0xa602487d; /* mflr r10				*/ \

	.long 0x1c004a39; /* addi r10,r10,28			*/ \

	b     $+44;	  /* Skip trampoline if endian is good	*/ \

	.long 0xa600607d; /* mfmsr r11				*/ \

	.long 0x01006b69; /* xori r11,r11,1			*/ \

	.long 0x00004039; /* li r10,0				*/ \

	.long 0x6401417d; /* mtmsrd r10,1			*/ \

	.long 0x05009f42; /* bcl 20,31,$+4			*/ \

	.long 0xa602487d; /* mflr r10				*/ \

	.long 0x14004a39; /* addi r10,r10,20			*/ \

	.long 0xa6035a7d; /* mtsrr0 r10				*/ \

	.long 0xa6037b7d; /* mtsrr1 r11				*/ \

	.long 0x2400004c  /* rfid				*/



#endif /* !CONFIG_PPC_BOOK3E */



#endif /*  __ASSEMBLY__ */