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Commit f1a9ba8f authored by Paul Mundt's avatar Paul Mundt
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sh: pci: drop duplicate PCIC fixups for SE7780 and SH7785LCR. 



SE7780 has the same PCIC fixup as SDK7780, and SH7785LCR the same
as R7780RP. Switch to using those, and drop the duplicate code.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 3aabce8d

arch/sh/drivers/pci/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -21,6 +21,6 @@ obj-$(CONFIG_SH_SDK7780) += ops-sdk7780.o fixups-sdk7780.o 
obj-$(CONFIG_SH_TITAN)			+= ops-titan.o

obj-$(CONFIG_SH_LANDISK)		+= ops-landisk.o

obj-$(CONFIG_SH_LBOX_RE2)		+= ops-lboxre2.o fixups-lboxre2.o

obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)	+= ops-se7780.o fixups-se7780.o

obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)	+= ops-se7780.o fixups-sdk7780.o

obj-$(CONFIG_SH_CAYMAN)			+= ops-cayman.o

obj-$(CONFIG_SH_SH7785LCR)		+= ops-sh7785lcr.o fixups-sh7785lcr.o
 
obj-$(CONFIG_SH_SH7785LCR)		+= ops-sh7785lcr.o fixups-r7780rp.o

arch/sh/drivers/pci/fixups-se7780.c

deleted100644 → 0
+0 −62
Original line number Diff line number Diff line 
/*

 * arch/sh/drivers/pci/fixups-se7780.c

 *

 * HITACHI UL Solution Engine 7780  PCI fixups

 *

 * Copyright (C) 2003  Lineo uSolutions, Inc.

 * Copyright (C) 2004 - 2006  Paul Mundt

 * Copyright (C) 2006  Nobuhiro Iwamatsu

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/pci.h>

#include "pci-sh4.h"

#include <asm/io.h>



int pci_fixup_pcic(struct pci_channel *chan)

{

	ctrl_outl(0x00000001, SH7780_PCI_VCR2);



	/* Enable all interrupts, so we know what to fix */

	pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);

	pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);



	/* Set up standard PCI config registers */

	ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));

	ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));

	ctrl_outb(  0x00, PCI_REG(SH7780_PCIPIF));

	ctrl_outb(  0x00, PCI_REG(SH7780_PCISUB));

	ctrl_outb(  0x06, PCI_REG(SH7780_PCIBCC));

	ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));

	ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));



	pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0);     /* PCI */

	pci_write_reg(chan, 0x08000000, SH7780_PCILAR0);     /* SHwy */

	pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */



	pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);

	pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);



	pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);



	/*

	 * Set the MBR so PCI address is one-to-one with window,

	 * meaning all calls go straight through... use ifdef to

	 * catch erroneous assumption.

	 */

	pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0);    /* 16M */



	/* Set IOBR for window containing area specified in pci.h */

	pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),

		      SH7780_PCIIOBMR);



	pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);



	return 0;

}

arch/sh/drivers/pci/fixups-sh7785lcr.c

deleted100644 → 0
+0 −47
Original line number Diff line number Diff line 
/*

 * arch/sh/drivers/pci/fixups-sh7785lcr.c

 *

 * R0P7785LC0011RL PCI fixups

 * Copyright (C) 2008  Yoshihiro Shimoda

 *

 * Based on arch/sh/drivers/pci/fixups-r7780rp.c

 * Copyright (C) 2003  Lineo uSolutions, Inc.

 * Copyright (C) 2004 - 2006  Paul Mundt

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/pci.h>

#include "pci-sh4.h"



int pci_fixup_pcic(struct pci_channel *chan)

{

	pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);

	pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);



	pci_write_reg(chan, 0xfbb00047, SH7780_PCICMD);

	pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);



	pci_write_reg(chan, 0x00011912, SH7780_PCISVID);

	pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);

	pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);

	pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);

	pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);



	pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);

	pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);



#ifdef CONFIG_32BIT

	pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);

	pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);

#endif



	/* Set IOBR for windows containing area specified in pci.h */

	pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE - 1),

		      SH7780_PCIIOBR);

	pci_write_reg(chan, ((SH7780_PCI_IO_SIZE - 1) & (7 << 18)),

		      SH7780_PCIIOBMR);



	return 0;

}