Merge back earlier cpuidle changes for v4.7. (f0fb0dd0) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/cpuidle/cpuidle.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -433,6 +433,8 @@ static void __cpuidle_unregister_device(struct cpuidle_device *dev)
		list_del(&dev->device_list);
		per_cpu(cpuidle_devices, dev->cpu) = NULL;
		module_put(drv->owner);

		dev->registered = 0;
		}

		static void __cpuidle_device_init(struct cpuidle_device *dev)

drivers/idle/intel_idle.c

+137 −0

Original line number	Diff line number	Diff line
		@@ -766,6 +766,67 @@ static struct cpuidle_state knl_cstates[] = {
		.enter = NULL }
		};

		static struct cpuidle_state bxt_cstates[] = {
		{
		.name = "C1-BXT",
		.desc = "MWAIT 0x00",
		.flags = MWAIT2flg(0x00),
		.exit_latency = 2,
		.target_residency = 2,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C1E-BXT",
		.desc = "MWAIT 0x01",
		.flags = MWAIT2flg(0x01),
		.exit_latency = 10,
		.target_residency = 20,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C6-BXT",
		.desc = "MWAIT 0x20",
		.flags = MWAIT2flg(0x20) \| CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 133,
		.target_residency = 133,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C7s-BXT",
		.desc = "MWAIT 0x31",
		.flags = MWAIT2flg(0x31) \| CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 155,
		.target_residency = 155,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C8-BXT",
		.desc = "MWAIT 0x40",
		.flags = MWAIT2flg(0x40) \| CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 1000,
		.target_residency = 1000,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C9-BXT",
		.desc = "MWAIT 0x50",
		.flags = MWAIT2flg(0x50) \| CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 2000,
		.target_residency = 2000,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.name = "C10-BXT",
		.desc = "MWAIT 0x60",
		.flags = MWAIT2flg(0x60) \| CPUIDLE_FLAG_TLB_FLUSHED,
		.exit_latency = 10000,
		.target_residency = 10000,
		.enter = &intel_idle,
		.enter_freeze = intel_idle_freeze, },
		{
		.enter = NULL }
		};

		/**
		* intel_idle
		* @dev: cpuidle_device
		@@ -950,6 +1011,11 @@ static const struct idle_cpu idle_cpu_knl = {
		.state_table = knl_cstates,
		};

		static const struct idle_cpu idle_cpu_bxt = {
		.state_table = bxt_cstates,
		.disable_promotion_to_c1e = true,
		};

		#define ICPU(model, cpu) \
		{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }

		@@ -985,6 +1051,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
		ICPU(0x9e, idle_cpu_skl),
		ICPU(0x55, idle_cpu_skx),
		ICPU(0x57, idle_cpu_knl),
		ICPU(0x5c, idle_cpu_bxt),
		{}
		};
		MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
		@@ -1075,6 +1142,73 @@ static void ivt_idle_state_table_update(void)

		/* else, 1 and 2 socket systems use default ivt_cstates */
		}

		/*
		* Translate IRTL (Interrupt Response Time Limit) MSR to usec
		*/

		static unsigned int irtl_ns_units[] = {
		1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };

		static unsigned long long irtl_2_usec(unsigned long long irtl)
		{
		unsigned long long ns;

		ns = irtl_ns_units[(irtl >> 10) & 0x3];

		return div64_u64((irtl & 0x3FF) * ns, 1000);
		}
		/*
		* bxt_idle_state_table_update(void)
		*
		* On BXT, we trust the IRTL to show the definitive maximum latency
		* We use the same value for target_residency.
		*/
		static void bxt_idle_state_table_update(void)
		{
		unsigned long long msr;

		rdmsrl(MSR_PKGC6_IRTL, msr);
		if (msr) {
		unsigned int usec = irtl_2_usec(msr);

		bxt_cstates[2].exit_latency = usec;
		bxt_cstates[2].target_residency = usec;
		}

		rdmsrl(MSR_PKGC7_IRTL, msr);
		if (msr) {
		unsigned int usec = irtl_2_usec(msr);

		bxt_cstates[3].exit_latency = usec;
		bxt_cstates[3].target_residency = usec;
		}

		rdmsrl(MSR_PKGC8_IRTL, msr);
		if (msr) {
		unsigned int usec = irtl_2_usec(msr);

		bxt_cstates[4].exit_latency = usec;
		bxt_cstates[4].target_residency = usec;
		}

		rdmsrl(MSR_PKGC9_IRTL, msr);
		if (msr) {
		unsigned int usec = irtl_2_usec(msr);

		bxt_cstates[5].exit_latency = usec;
		bxt_cstates[5].target_residency = usec;
		}

		rdmsrl(MSR_PKGC10_IRTL, msr);
		if (msr) {
		unsigned int usec = irtl_2_usec(msr);

		bxt_cstates[6].exit_latency = usec;
		bxt_cstates[6].target_residency = usec;
		}

		}
		/*
		* sklh_idle_state_table_update(void)
		*
		@@ -1130,6 +1264,9 @@ static void intel_idle_state_table_update(void)
		case 0x3e: /* IVT */
		ivt_idle_state_table_update();
		break;
		case 0x5c: /* BXT */
		bxt_idle_state_table_update();
		break;
		case 0x5e: /* SKL-H */
		sklh_idle_state_table_update();
		break;