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Commit f088a101 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: msm: Enable arm64 cortex edac support for bengal"

parents 20a1caf1 8ebd8715

arch/arm64/configs/vendor/bengal_defconfig

+3 −0
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@@ -402,6 +402,9 @@ CONFIG_MMC_SDHCI=y 
CONFIG_MMC_SDHCI_PLTFM=y

CONFIG_MMC_SDHCI_MSM=y

CONFIG_EDAC=y

CONFIG_EDAC_CORTEX_ARM64=y

CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY=y

CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE=y

CONFIG_RTC_CLASS=y

CONFIG_DMADEVICES=y

CONFIG_QCOM_GPI_DMA=y

arch/arm64/include/asm/edac.h

0 → 100644
+26 −0
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/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef ASM_EDAC_H

#define ASM_EDAC_H



#if defined(CONFIG_EDAC_CORTEX_ARM64) && \

	!defined(CONFIG_EDAC_CORTEX_ARM64_DBE_IRQ_ONLY)

void arm64_check_cache_ecc(void *info);

#else

static inline void arm64_check_cache_ecc(void *info) { }

#endif



static inline void atomic_scrub(void *addr, int size) { }



#endif

drivers/edac/Kconfig

+40 −0
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@@ -501,6 +501,46 @@ config EDAC_TI 
	  Support for error detection and correction on the

          TI SoCs.



config EDAC_CORTEX_ARM64

	depends on ARM64

	bool "ARM Cortex A CPUs L1/L2 Caches"

	help

	  Support for error detection and correction on the

	  ARM Cortex A53 and A57 CPUs. For debugging issues having to do with

	  stability and overall system health, you should probably say 'Y'

	  here.



config EDAC_CORTEX_ARM64_PANIC_ON_CE

	depends on EDAC_CORTEX_ARM64

	bool "Panic on correctable errors"

	help

	  Forcibly cause a kernel panic if an correctable error (CE) is

	  detected, even though the error is (by definition) correctable and

	  would otherwise result in no adverse system effects. This can reduce

	  debugging times on hardware which may be operating at voltages or

	  frequencies outside normal specification.



	  For production builds, you should definitely say 'N' here.



config EDAC_CORTEX_ARM64_DBE_IRQ_ONLY

	depends on EDAC_CORTEX_ARM64

	bool "Only check for parity errors when an irq is generated"

	help

	  In ARM64, parity errors will cause an interrupt

	  to be triggered but may also cause a data abort to

	  occur. Only check for EDAC errors for the interrupt.

	  If unsure, say no.



config EDAC_CORTEX_ARM64_PANIC_ON_UE

	depends on EDAC_CORTEX_ARM64

	bool "Panic on uncorrectable errors"

	help

	  Forcibly cause a kernel panic if an uncorrectable error (UE) is

	  detected. This can reduce debugging times on hardware which may be

	  operating at voltages or frequencies outside normal specification.



	  For production builds, you should probably say 'N' here.



config EDAC_QCOM

	tristate "QCOM EDAC Controller"

	depends on ARCH_QCOM && QCOM_LLCC

drivers/edac/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -79,3 +79,4 @@ obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o 
obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o

obj-$(CONFIG_EDAC_TI)			+= ti_edac.o

obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o

obj-$(CONFIG_EDAC_CORTEX_ARM64)		+= cortex_arm64_edac.o