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Commit efcac658 authored by Alexey Kardashevskiy's avatar Alexey Kardashevskiy Committed by Benjamin Herrenschmidt
Browse files

powerpc: Per process DSCR + some fixes (try#4) 



The DSCR (aka Data Stream Control Register) is supported on some
server PowerPC chips and allow some control over the prefetch
of data streams.

This patch allows the value to be specified per thread by emulating
the corresponding mfspr and mtspr instructions. Children of such
threads inherit the value. Other threads use a default value that
can be specified in sysfs - /sys/devices/system/cpu/dscr_default.

If a thread starts with non default value in the sysfs entry,
all children threads inherit this non default value even if
the sysfs value is changed later.

Signed-off-by: default avatarAlexey Kardashevskiy <aik@au1.ibm.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent f0aae323

arch/powerpc/include/asm/emulated_ops.h

+4 −0
Original line number Diff line number Diff line
@@ -52,6 +52,10 @@ extern struct ppc_emulated { 
#ifdef CONFIG_VSX

	struct ppc_emulated_entry vsx;

#endif

#ifdef CONFIG_PPC64

	struct ppc_emulated_entry mfdscr;

	struct ppc_emulated_entry mtdscr;

#endif

} ppc_emulated;



extern u32 ppc_warn_emulated;

arch/powerpc/include/asm/ppc-opcode.h

+4 −0
Original line number Diff line number Diff line
@@ -41,6 +41,10 @@ 
#define PPC_INST_RFCI			0x4c000066

#define PPC_INST_RFDI			0x4c00004e

#define PPC_INST_RFMCI			0x4c00004c

#define PPC_INST_MFSPR_DSCR		0x7c1102a6

#define PPC_INST_MFSPR_DSCR_MASK	0xfc1fffff

#define PPC_INST_MTSPR_DSCR		0x7c1103a6

#define PPC_INST_MTSPR_DSCR_MASK	0xfc1fffff



#define PPC_INST_STRING			0x7c00042a

#define PPC_INST_STRING_MASK		0xfc0007fe

arch/powerpc/include/asm/processor.h

+4 −0
Original line number Diff line number Diff line
@@ -238,6 +238,10 @@ struct thread_struct { 
#ifdef CONFIG_KVM_BOOK3S_32_HANDLER

	void*		kvm_shadow_vcpu; /* KVM internal data */

#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */

#ifdef CONFIG_PPC64

	unsigned long	dscr;

	int		dscr_inherit;

#endif

};



#define ARCH_MIN_TASKALIGN 16

arch/powerpc/kernel/asm-offsets.c

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ int main(void) 
	DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));

	DEFINE(SIGSEGV, SIGSEGV);

	DEFINE(NMI_MASK, NMI_MASK);

	DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));

#else

	DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));

#endif /* CONFIG_PPC64 */

arch/powerpc/kernel/entry_64.S

+15 −0
Original line number Diff line number Diff line
@@ -421,6 +421,12 @@ BEGIN_FTR_SECTION 
	std	r24,THREAD_VRSAVE(r3)

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif /* CONFIG_ALTIVEC */

#ifdef CONFIG_PPC64

BEGIN_FTR_SECTION

	mfspr	r25,SPRN_DSCR

	std	r25,THREAD_DSCR(r3)

END_FTR_SECTION_IFSET(CPU_FTR_DSCR)

#endif

	and.	r0,r0,r22

	beq+	1f

	andc	r22,r22,r0
@@ -522,6 +528,15 @@ BEGIN_FTR_SECTION 
	mtspr	SPRN_VRSAVE,r0		/* if G4, restore VRSAVE reg */

END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)

#endif /* CONFIG_ALTIVEC */

#ifdef CONFIG_PPC64

BEGIN_FTR_SECTION

	ld	r0,THREAD_DSCR(r4)

	cmpd	r0,r25

	beq	1f

	mtspr	SPRN_DSCR,r0

1:	

END_FTR_SECTION_IFSET(CPU_FTR_DSCR)

#endif



	/* r3-r13 are destroyed -- Cort */

	REST_8GPRS(14, r1)