Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit eee41b49 authored by Shengzhou Liu's avatar Shengzhou Liu Committed by Greg Kroah-Hartman
Browse files

USB: fsl/ehci: fix failure of checking PHY_CLK_VALID during reinitialization 



In case of usb phy reinitialization:
e.g. insmod usb-module(usb works well) -> rmmod usb-module -> insmod usb-module
It found the PHY_CLK_VALID bit didn't work if it's not with the power-on reset.
So we just check PHY_CLK_VALID bit during the stage with POR, this can be met
by the tricky of checking FSL_SOC_USB_PRICTRL register.

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2606b28a

drivers/usb/host/ehci-fsl.c

+3 −2
Original line number Diff line number Diff line
@@ -264,8 +264,9 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	if (pdata->have_sysif_regs && pdata->controller_ver &&

	    (phy_mode == FSL_USB2_PHY_ULPI)) {

		/* check PHY_CLK_VALID to get phy clk valid */

		if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &

				PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {

		if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &

				PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||

				in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {

			printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");

			return -EINVAL;

		}