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Commit ee73164a authored by Pixel Ding's avatar Pixel Ding Committed by Alex Deucher
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drm/amdgpu/virt: don't check VALID bit for FLR completion message 



The interrupt after FLR is missed sometimes due to hardware reason, so
guest driver get the notification of FLR completion via polling
message. Then host doesn't write VALID bit to avoid sending interrupt,
otherwise the completion will be handled twice.

So there's a valid message without VALID bit for FLR completion,
driver should handle it without checking.

Signed-off-by: default avatarPixel Ding <Pixel.Ding@amd.com>
Reviewed-by: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ad2fed9a

drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c

+6 −3
Original line number Original line Diff line number Diff line
@@ -368,9 +368,12 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev, 
	u32 reg;

	u32 reg;

	u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);

	u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);





	/* workaround: host driver doesn't set VALID for CMPL now */

	if (event != IDH_FLR_NOTIFICATION_CMPL) {

		reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

		reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL);

		if (!(reg & mask))

		if (!(reg & mask))

			return -ENOENT;

			return -ENOENT;

	}





	reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

	reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0);

	if (reg != event)

	if (reg != event)