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Commit ee2b0b38 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: add haswell_set_pipeconf 



It's a copy of ironlake_set_pipeconf with 2 differences:
  - There is no BPC field to set.
  - The interlaced mask is now 2 bits instead of 3.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5dc5298b

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -2639,6 +2639,7 @@ 
#define   PIPECONF_GAMMA		(1<<24)

#define   PIPECONF_FORCE_BORDER	(1<<25)

#define   PIPECONF_INTERLACE_MASK	(7 << 21)

#define   PIPECONF_INTERLACE_MASK_HSW	(3 << 21)

/* Note that pre-gen3 does not support interlaced display directly. Panel

 * fitting must be disabled on pre-ilk for interlaced. */

#define   PIPECONF_PROGRESSIVE			(0 << 21)

drivers/gpu/drm/i915/intel_display.c

+26 −1
Original line number Diff line number Diff line
@@ -4721,6 +4721,31 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, 
	POSTING_READ(PIPECONF(pipe));

}



static void haswell_set_pipeconf(struct drm_crtc *crtc,

				 struct drm_display_mode *adjusted_mode,

				 bool dither)

{

	struct drm_i915_private *dev_priv = crtc->dev->dev_private;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	int pipe = intel_crtc->pipe;

	uint32_t val;



	val = I915_READ(PIPECONF(pipe));



	val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);

	if (dither)

		val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);



	val &= ~PIPECONF_INTERLACE_MASK_HSW;

	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)

		val |= PIPECONF_INTERLACED_ILK;

	else

		val |= PIPECONF_PROGRESSIVE;



	I915_WRITE(PIPECONF(pipe), val);

	POSTING_READ(PIPECONF(pipe));

}



static bool ironlake_compute_clocks(struct drm_crtc *crtc,

				    struct drm_display_mode *adjusted_mode,

				    intel_clock_t *clock,
@@ -5322,7 +5347,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, 
		if (is_cpu_edp)

			ironlake_set_pll_edp(crtc, adjusted_mode->clock);



	ironlake_set_pipeconf(crtc, adjusted_mode, dither);

	haswell_set_pipeconf(crtc, adjusted_mode, dither);



	intel_wait_for_vblank(dev, pipe);