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Commit edfaf05c authored by Victor Kamensky's avatar Victor Kamensky Committed by Tony Lindgren
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ARM: OMAP2+: raw read and write endian fix 



All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.

Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.

Signed-off-by: default avatarVictor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: default avatarTaras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 89ca3b88

arch/arm/mach-omap2/board-flash.c

+2 −2
Original line number Diff line number Diff line
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void) 
	if (!fpga_map_addr)

		return -ENOMEM;



	if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))

	if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))

		/* we dont have an DEBUG FPGA??? */

		/* Depend on #defines!! default to strata boot return param */

		goto unmap;



	/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */

	cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;

	cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;



	/* ES2.0 SDP's onwards 4 dip switches are provided for CS */

	if (omap_rev() >= OMAP3430_REV_ES1_0)

arch/arm/mach-omap2/clkt2xxx_dpllcore.c

+1 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, 
		if (!dd)

			return -EINVAL;



		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);

		tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);

		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |

					   dd->div1_mask);

		div = ((curr_prcm_set->xtal_speed / 1000000) - 1);

arch/arm/mach-omap2/clkt2xxx_osc.c

+4 −4
Original line number Diff line number Diff line
@@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk) 
{

	u32 pcc;



	pcc = __raw_readl(prcm_clksrc_ctrl);

	pcc = readl_relaxed(prcm_clksrc_ctrl);



	__raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);

	writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);



	return 0;

}
@@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk) 
{

	u32 pcc;



	pcc = __raw_readl(prcm_clksrc_ctrl);

	pcc = readl_relaxed(prcm_clksrc_ctrl);



	__raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);

	writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);

}



unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,

arch/arm/mach-omap2/clkt2xxx_sys.c

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void) 
{

	u32 div;



	div = __raw_readl(prcm_clksrc_ctrl);

	div = readl_relaxed(prcm_clksrc_ctrl);

	div &= OMAP_SYSCLKDIV_MASK;

	div >>= OMAP_SYSCLKDIV_SHIFT;

arch/arm/mach-omap2/cm2xxx_3xxx.h

+2 −2
Original line number Diff line number Diff line
@@ -52,12 +52,12 @@ 


static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)

{

	return __raw_readl(cm_base + module + idx);

	return readl_relaxed(cm_base + module + idx);

}



static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)

{

	__raw_writel(val, cm_base + module + idx);

	writel_relaxed(val, cm_base + module + idx);

}



/* Read-modify-write a register in a CM module. Caller must lock */