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Commit edb2a385 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v4.18.

  No core changes this time! Just a calm all-over-the-place drivers,
  updates and fixes cycle as it seems.

  New drivers/subdrivers:

   - Actions Semiconductor S900 driver with more Actions variants for
     S700, S500 in the pipe. Also generic GPIO support on top of the
     same driver and IRQ support is in the pipe.

   - Renesas r8a77470 PFC support.

   - Renesas r8a77990 PFC support.

   - Allwinner Sunxi H6 R_PIO support.

   - Rockchip PX30 support.

   - Meson Meson8m2 support.

   - Remove support for the ill-fated Samsung Exynos 5440 SoC.

  Improvements:

   - Context save/restore support in pinctrl-single.

   - External interrupt support for the Mediatek MT7622.

   - Qualcomm ACPI HID QCOM8002 supported.

  Fixes:

   - Fix up suspend/resume support for Exynos 5433.

   - Fix Strago DMI fixes on the Intel Cherryview"

* tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: cherryview: limit Strago DMI workarounds to version 1.0
  pinctrl: at91-pio4: add missing of_node_put
  pinctrl: armada-37xx: Fix spurious irq management
  gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrls
  pinctrl: msm: fix gpio-hog related boot issues
  MAINTAINERS: update entry for Mediatek pin controller
  pinctrl: mediatek: remove unused fields in struct mtk_eint_hw
  pinctrl: mediatek: use generic EINT register maps for each SoC
  pinctrl: mediatek: add EINT support to MT7622 SoC
  pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit
  dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrl
  pinctrl: freescale: Switch to SPDX identifier
  pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banks
  pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin comments
  pinctrl: sh-pfc: r8a77965: Add I2C pin support
  pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add bias pinconf support
  pinctrl: sh-pfc: Initial R8A77990 PFC support
  ...
parents 3a979e8c 86c5dd68
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+16 −0
Original line number Diff line number Diff line
@@ -8,6 +8,17 @@ Required Properties:
- reg:          Should contain the register base address and size of
                the pin controller.
- clocks:       phandle of the clock feeding the pin controller
- gpio-controller: Marks the device node as a GPIO controller.
- gpio-ranges: Specifies the mapping between gpio controller and
               pin-controller pins.
- #gpio-cells: Should be two. The first cell is the gpio pin number
               and the second cell is used for optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
                    interrupt.  Shall be set to 2.  The first cell
                    defines the interrupt number, the second encodes
                    the trigger flags described in
                    bindings/interrupt-controller/interrupts.txt

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -164,6 +175,11 @@ Example:
                  compatible = "actions,s900-pinctrl";
                  reg = <0x0 0xe01b0000 0x0 0x1000>;
                  clocks = <&cmu CLK_GPIO>;
                  gpio-controller;
                  gpio-ranges = <&pinctrl 0 0 146>;
                  #gpio-cells = <2>;
                  interrupt-controller;
                  #interrupt-cells = <2>;

                  uart2-default: uart2-default {
                          pinmux {
+1 −0
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@@ -28,6 +28,7 @@ Required properties:
  "allwinner,sun50i-a64-r-pinctrl"
  "allwinner,sun50i-h5-pinctrl"
  "allwinner,sun50i-h6-pinctrl"
  "allwinner,sun50i-h6-r-pinctrl"
  "nextthing,gr8-pinctrl"

- reg: Should contain the register physical address and length for the
+18 −0
Original line number Diff line number Diff line
@@ -36,6 +36,24 @@ listed. In other words, a subnode that lists only a mux function implies no
information about any pull configuration. Similarly, a subnode that lists only
a pul parameter implies no information about the mux function.

The BCM2835 pin configuration and multiplexing supports the generic bindings.
For details on each properties, you can refer to ./pinctrl-bindings.txt.

Required sub-node properties:
  - pins
  - function

Optional sub-node properties:
  - bias-disable
  - bias-pull-up
  - bias-pull-down
  - output-high
  - output-low

Legacy pin configuration and multiplexing binding:
*** (Its use is deprecated, use generic multiplexing and configuration
bindings instead)

Required subnode-properties:
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
  are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
+2 −0
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@@ -3,8 +3,10 @@
Required properties for the root node:
 - compatible: one of "amlogic,meson8-cbus-pinctrl"
		      "amlogic,meson8b-cbus-pinctrl"
		      "amlogic,meson8m2-cbus-pinctrl"
		      "amlogic,meson8-aobus-pinctrl"
		      "amlogic,meson8b-aobus-pinctrl"
		      "amlogic,meson8m2-aobus-pinctrl"
		      "amlogic,meson-gxbb-periphs-pinctrl"
		      "amlogic,meson-gxbb-aobus-pinctrl"
		      "amlogic,meson-gxl-periphs-pinctrl"
+3 −1
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@@ -18,7 +18,9 @@ Required properties:
    removed.
- #gpio-cells : Should be two.
  - first cell is the pin number
  - second cell is used to specify flags. Flags are currently unused.
  - second cell is used to specify flags as described in
    'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
    'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
- gpio-controller : Marks the device node as a GPIO controller.
- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
        SPI uses this to specify the chipselect line which the chip is
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