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Commit edae583a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-v3.13-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC changes from Vineet Gupta:
 - Towards a working SMP setup (ASID allocation, TLB Flush,...)
 - Support for TRACE_IRQFLAGS, LOCKDEP
 - cacheflush backend consolidation for I/D
 - Lots of allmodconfig fixlets from Chen
 - Other improvements/fixes

* tag 'arc-v3.13-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (25 commits)
  ARC: [plat-arcfpga] defconfig update
  smp, ARC: kill SMP single function call interrupt
  ARC: [SMP] Disallow RTSC
  ARC: [SMP] Fix build failures for large NR_CPUS
  ARC: [SMP] enlarge possible NR_CPUS
  ARC: [SMP] TLB flush
  ARC: [SMP] ASID allocation
  arc: export symbol for pm_power_off in reset.c
  arc: export symbol for save_stack_trace() in stacktrace.c
  arc: remove '__init' for get_hw_config_num_irq()
  arc: remove '__init' for first_lines_of_secondary()
  arc: remove '__init' for setup_processor() and arc_init_IRQ()
  arc: kgdb: add default implementation for kgdb_roundup_cpus()
  ARC: Fix bogus gcc warning and micro-optimise TLB iteration loop
  ARC: Add support for irqflags tracing and lockdep
  ARC: Reset the value of Interrupt Priority Register
  ARC: Reduce #ifdef'ery for unaligned access emulation
  ARC: Change calling convention of do_page_fault()
  ARC: cacheflush optim - PTAG can be loop invariant if V-P is const
  ARC: cacheflush refactor #3: Unify the {d,i}cache flush leaf helpers
  ...
parents 0a759b24 737d5b98

arch/arc/Kconfig

+9 −7
Original line number Original line Diff line number Diff line
@@ -35,6 +35,12 @@ config ARC 
	select PERF_USE_VMALLOC

	select PERF_USE_VMALLOC

	select HAVE_DEBUG_STACKOVERFLOW

	select HAVE_DEBUG_STACKOVERFLOW





config TRACE_IRQFLAGS_SUPPORT

	def_bool y



config LOCKDEP_SUPPORT

	def_bool y



config SCHED_OMIT_FRAME_POINTER

config SCHED_OMIT_FRAME_POINTER

	def_bool y

	def_bool y
@@ -130,17 +136,14 @@ if SMP 
config ARC_HAS_COH_CACHES

config ARC_HAS_COH_CACHES

	def_bool n

	def_bool n





config ARC_HAS_COH_RTSC

	def_bool n



config ARC_HAS_REENTRANT_IRQ_LV2

config ARC_HAS_REENTRANT_IRQ_LV2

	def_bool n

	def_bool n





endif

endif





config NR_CPUS

config NR_CPUS

	int "Maximum number of CPUs (2-32)"

	int "Maximum number of CPUs (2-4096)"

	range 2 32

	range 2 4096

	depends on SMP

	depends on SMP

	default "2"

	default "2"
@@ -326,8 +329,7 @@ config ARC_HAS_RTSC 
	bool "Insn: RTSC (64-bit r/o cycle counter)"

	bool "Insn: RTSC (64-bit r/o cycle counter)"

	default y

	default y

	depends on ARC_CPU_REL_4_10

	depends on ARC_CPU_REL_4_10

	# if SMP, enable RTSC only if counter is coherent across cores

	depends on !SMP

	depends on !SMP || ARC_HAS_COH_RTSC





endmenu   # "ARC CPU Configuration"

endmenu   # "ARC CPU Configuration"

arch/arc/configs/fpga_defconfig

+3 −0
Original line number Original line Diff line number Diff line
@@ -2,6 +2,8 @@ CONFIG_CROSS_COMPILE="arc-linux-uclibc-" 
# CONFIG_LOCALVERSION_AUTO is not set

# CONFIG_LOCALVERSION_AUTO is not set

CONFIG_DEFAULT_HOSTNAME="ARCLinux"

CONFIG_DEFAULT_HOSTNAME="ARCLinux"

# CONFIG_SWAP is not set

# CONFIG_SWAP is not set

CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_IKCONFIG_PROC=y
@@ -62,4 +64,5 @@ CONFIG_TMPFS=y 
CONFIG_NFS_FS=y

CONFIG_NFS_FS=y

# CONFIG_ENABLE_WARN_DEPRECATED is not set

# CONFIG_ENABLE_WARN_DEPRECATED is not set

# CONFIG_ENABLE_MUST_CHECK is not set

# CONFIG_ENABLE_MUST_CHECK is not set

# CONFIG_DEBUG_PREEMPT is not set

CONFIG_XZ_DEC=y
 
CONFIG_XZ_DEC=y

arch/arc/include/asm/cache.h

+1 −7
Original line number Original line Diff line number Diff line
@@ -17,13 +17,7 @@ 
#endif

#endif





#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



#define CACHE_LINE_MASK		(~(L1_CACHE_BYTES - 1))

/* For a rare case where customers have differently config I/D */

#define ARC_ICACHE_LINE_LEN	L1_CACHE_BYTES

#define ARC_DCACHE_LINE_LEN	L1_CACHE_BYTES



#define ICACHE_LINE_MASK	(~(ARC_ICACHE_LINE_LEN - 1))

#define DCACHE_LINE_MASK	(~(ARC_DCACHE_LINE_LEN - 1))





/*

/*

 * ARC700 doesn't cache any access in top 256M.

 * ARC700 doesn't cache any access in top 256M.

arch/arc/include/asm/irq.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -18,8 +18,8 @@ 




#include <asm-generic/irq.h>

#include <asm-generic/irq.h>





extern void __init arc_init_IRQ(void);

extern void arc_init_IRQ(void);

extern int __init get_hw_config_num_irq(void);

extern int get_hw_config_num_irq(void);





void arc_local_timer_setup(unsigned int cpu);

void arc_local_timer_setup(unsigned int cpu);

arch/arc/include/asm/irqflags.h

+22 −0
Original line number Original line Diff line number Diff line
@@ -151,16 +151,38 @@ static inline void arch_unmask_irq(unsigned int irq) 




#else

#else





#ifdef CONFIG_TRACE_IRQFLAGS



.macro TRACE_ASM_IRQ_DISABLE

	bl	trace_hardirqs_off

.endm



.macro TRACE_ASM_IRQ_ENABLE

	bl	trace_hardirqs_on

.endm



#else



.macro TRACE_ASM_IRQ_DISABLE

.endm



.macro TRACE_ASM_IRQ_ENABLE

.endm



#endif



.macro IRQ_DISABLE  scratch

.macro IRQ_DISABLE  scratch

	lr	\scratch, [status32]

	lr	\scratch, [status32]

	bic	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	bic	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	flag	\scratch

	flag	\scratch

	TRACE_ASM_IRQ_DISABLE

.endm

.endm





.macro IRQ_ENABLE  scratch

.macro IRQ_ENABLE  scratch

	lr	\scratch, [status32]

	lr	\scratch, [status32]

	or	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	or	\scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK)

	flag	\scratch

	flag	\scratch

	TRACE_ASM_IRQ_ENABLE

.endm

.endm





#endif	/* __ASSEMBLY__ */

#endif	/* __ASSEMBLY__ */