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Commit eceb55a0 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

This time around we have a mix of new hw enablement (mdp5 v1.3 /
apq8084), plus devicetree and various upstream changes (mostly
adapting to CCF vs downstream clk driver differences) for mdp4 /
apq8064.  With these drm/msm patches plus a few other small patchsets
(from linaro qcom integration branch.. mostly stuff queued up for
3.17) we have the inforce ifc6410 board working, with gpu.  Much nicer
to work with than ancient vendor android branch :-)

* 'msm-next' of git://people.freedesktop.org/~robclark/linux:
  drm/msm/hdmi: fix HDMI_MUX_EN gpio request typo
  drm/msm/hdmi: enable lpm-mux if it is present
  drm/msm/mdp5: add support for MDP5 v1.3
  drm/msm: fix potential deadlock in gpu init
  drm/msm: use upstream iommu
  drm/msm: no mmu is only error if not using vram carveout
  drm/msm: fix BUG_ON() in error cleanup path
  drm/msm/mdp4: add mdp axi clk
  drm/msm: hdmi phy 8960 phy pll
  drm/msm: update generated headers
  drm/msm: DT support for 8960/8064 (v3)
  drm/msm: Implement msm drm fb_mmap callback function
  drm/msm: activate iommu support
  drm/msm: fix double struct_mutex acquire
parents 5d42f82a a2fe6cdc

Documentation/devicetree/bindings/drm/msm/gpu.txt

0 → 100644
+52 −0
Original line number Diff line number Diff line 
Qualcomm adreno/snapdragon GPU



Required properties:

- compatible: "qcom,adreno-3xx"

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the gpu.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "mem_iface_clk"

- qcom,chipid: gpu chip-id.  Note this may become optional for future

  devices if we can reliably read the chipid from hw

- qcom,gpu-pwrlevels: list of operating points

  - compatible: "qcom,gpu-pwrlevels"

  - for each qcom,gpu-pwrlevel:

    - qcom,gpu-freq: requested gpu clock speed

    - NOTE: downstream android driver defines additional parameters to

      configure memory bandwidth scaling per OPP.



Example:



/ {

	...



	gpu: qcom,kgsl-3d0@4300000 {

		compatible = "qcom,adreno-3xx";

		reg = <0x04300000 0x20000>;

		reg-names = "kgsl_3d0_reg_memory";

		interrupts = <GIC_SPI 80 0>;

		interrupt-names = "kgsl_3d0_irq";

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "mem_iface_clk";

		clocks =

		    <&mmcc GFX3D_CLK>,

		    <&mmcc GFX3D_AHB_CLK>,

		    <&mmcc MMSS_IMEM_AHB_CLK>;

		qcom,chipid = <0x03020100>;

		qcom,gpu-pwrlevels {

			compatible = "qcom,gpu-pwrlevels";

			qcom,gpu-pwrlevel@0 {

				qcom,gpu-freq = <450000000>;

			};

			qcom,gpu-pwrlevel@1 {

				qcom,gpu-freq = <27000000>;

			};

		};

	};

};

Documentation/devicetree/bindings/drm/msm/hdmi.txt

0 → 100644
+46 −0
Original line number Diff line number Diff line 
Qualcomm adreno/snapdragon hdmi output



Required properties:

- compatible: one of the following

   * "qcom,hdmi-tx-8660"

   * "qcom,hdmi-tx-8960"

- reg: Physical base address and length of the controller's registers

- reg-names: "core_physical"

- interrupts: The interrupt signal from the hdmi block.

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin

- qcom,hdmi-tx-ddc-data-gpio: ddc data pin

- qcom,hdmi-tx-hpd-gpio: hpd pin

- core-vdda-supply: phandle to supply regulator

- hdmi-mux-supply: phandle to mux regulator



Optional properties:

- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin

- qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin



Example:



/ {

	...



	hdmi: qcom,hdmi-tx-8960@4a00000 {

		compatible = "qcom,hdmi-tx-8960";

		reg-names = "core_physical";

		reg = <0x04a00000 0x1000>;

		interrupts = <GIC_SPI 79 0>;

		clock-names =

		    "core_clk",

		    "master_iface_clk",

		    "slave_iface_clk";

		clocks =

		    <&mmcc HDMI_APP_CLK>,

		    <&mmcc HDMI_M_AHB_CLK>,

		    <&mmcc HDMI_S_AHB_CLK>;

		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;

		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;

		core-vdda-supply = <&pm8921_hdmi_mvs>;

		hdmi-mux-supply = <&ext_3p3v>;

	};

};

Documentation/devicetree/bindings/drm/msm/mdp.txt

0 → 100644
+48 −0
Original line number Diff line number Diff line 
Qualcomm adreno/snapdragon display controller



Required properties:

- compatible:

  * "qcom,mdp" - mdp4

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- connectors: array of phandles for output device(s)

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

  * "core_clk"

  * "iface_clk"

  * "lut_clk"

  * "src_clk"

  * "hdmi_clk"

  * "mpd_clk"



Optional properties:

- gpus: phandle for gpu device



Example:



/ {

	...



	mdp: qcom,mdp@5100000 {

		compatible = "qcom,mdp";

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		connectors = <&hdmi>;

		gpus = <&gpu>;

		clock-names =

		    "core_clk",

		    "iface_clk",

		    "lut_clk",

		    "src_clk",

		    "hdmi_clk",

		    "mdp_clk";

		clocks =

		    <&mmcc MDP_SRC>,

		    <&mmcc MDP_AHB_CLK>,

		    <&mmcc MDP_LUT_CLK>,

		    <&mmcc TV_SRC>,

		    <&mmcc HDMI_TV_CLK>,

		    <&mmcc MDP_TV_CLK>;

	};

};

drivers/gpu/drm/msm/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
config DRM_MSM

	tristate "MSM DRM"

	depends on DRM

	depends on MSM_IOMMU

	depends on ARCH_QCOM || (ARM && COMPILE_TEST)

	select DRM_KMS_HELPER

	select SHMEM

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+50 −8
Original line number Diff line number Diff line
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git 
The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)



Copyright (C) 2013 by the following authors:

Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select { 
	SAMPLE_0123 = 6,

};



enum a2xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_MIN_DST_SRC = 2,

	BLEND_MAX_DST_SRC = 3,

	BLEND_DST_MINUS_SRC = 4,

	BLEND_DST_PLUS_SRC_BIAS = 5,

};



enum adreno_mmu_clnt_beh {

	BEH_NEVR = 0,

	BEH_TRAN_RNG = 1,
@@ -890,6 +899,39 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 
#define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9



#define REG_A2XX_VGT_DRAW_INITIATOR				0x000021fc

#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f

#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0

#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600

#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800

#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000

#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000

#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK		0xffff0000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT		16

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;

}



#define REG_A2XX_VGT_IMMED_DATA					0x000021fd
@@ -963,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend 
}

#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0

#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5

static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)

static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)

{

	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;

}
@@ -981,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend 
}

#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000

#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21

static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)

static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)

{

	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;

}