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Commit ec9dcd35 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'w5100-spi-and-w5200-support' 



Akinobu Mita says:

====================
net: w5100: add support W5100/W5200 for SPI interface

This series add support for Wiznet W5100 and W5200 for SPI interface.

We can easily find the ethernet modules and shield for Arduino with
these chips for purchase.  I've tested them with BeagleBone.

Wiznet W5100 for mmio access has already supported by w5100 driver.

In order to share the code between mmio mode and SPI mode, this series
firstly adds ability to support another register access interface to
the existing w5100 driver.  This ground work also requires to introduce
workqueue and threaded irq because SPI transfers are callable only from
contexts that can sleep unlike mmio access.

The latter part of this series adds w5100-spi driver which actually
support W5100 and W5200 for SPI interface.  Supporting W5100 is
straight forward because it only required to add a register access
interface by the SPI transfer.  W5100 and W5200 have similar memory
map which justifies adding W5200 support to w5100 driver.

* Changes from v2 to v3
- Add comment for reg_lock
- Add ability to allocate ops specific data structure
- Allocate w5200 ops specific data structure to put DMA-safe buffer
- Add missing chip_id assignment for w5100_*_ops

* Changes from v1 to v2
- Use a plain single pointer instead of SKB queue, spotted by David S. Miller
- Correct timeout period in w5100_command
- Use spi_write_then_read instead of spi_write which needs DMA-safe buffer
- Support W5200
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 544a773a 0c165ff2

drivers/net/ethernet/wiznet/Kconfig

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Original line number Diff line number Diff line
@@ -69,4 +69,18 @@ config WIZNET_BUS_ANY 
	  Performance may decrease compared to explicitly selected bus mode.

endchoice



config WIZNET_W5100_SPI

	tristate "WIZnet W5100/W5200 Ethernet support for SPI mode"

	depends on WIZNET_BUS_ANY

	depends on SPI

	---help---

	  In SPI mode host system accesses registers using SPI protocol

	  (mode 0) on the SPI bus.



	  Performance decreases compared to other bus interface mode.

	  In W5100 SPI mode, burst READ/WRITE processing are not provided.



	  To compile this driver as a module, choose M here: the module

	  will be called w5100-spi.



endif # NET_VENDOR_WIZNET

drivers/net/ethernet/wiznet/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_WIZNET_W5100) += w5100.o

obj-$(CONFIG_WIZNET_W5100_SPI) += w5100-spi.o

obj-$(CONFIG_WIZNET_W5300) += w5300.o

drivers/net/ethernet/wiznet/w5100-spi.c

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/*

 * Ethernet driver for the WIZnet W5100/W5200 chip.

 *

 * Copyright (C) 2016 Akinobu Mita <akinobu.mita@gmail.com>

 *

 * Licensed under the GPL-2 or later.

 *

 * Datasheet:

 * http://www.wiznet.co.kr/wp-content/uploads/wiznethome/Chip/W5100/Document/W5100_Datasheet_v1.2.6.pdf

 * http://wiznethome.cafe24.com/wp-content/uploads/wiznethome/Chip/W5200/Documents/W5200_DS_V140E.pdf

 */



#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/delay.h>

#include <linux/netdevice.h>

#include <linux/spi/spi.h>



#include "w5100.h"



#define W5100_SPI_WRITE_OPCODE 0xf0

#define W5100_SPI_READ_OPCODE 0x0f



static int w5100_spi_read(struct net_device *ndev, u16 addr)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[3] = { W5100_SPI_READ_OPCODE, addr >> 8, addr & 0xff };

	u8 data;

	int ret;



	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);



	return ret ? ret : data;

}



static int w5100_spi_write(struct net_device *ndev, u16 addr, u8 data)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[4] = { W5100_SPI_WRITE_OPCODE, addr >> 8, addr & 0xff, data};



	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);

}



static int w5100_spi_read16(struct net_device *ndev, u16 addr)

{

	u16 data;

	int ret;



	ret = w5100_spi_read(ndev, addr);

	if (ret < 0)

		return ret;

	data = ret << 8;

	ret = w5100_spi_read(ndev, addr + 1);



	return ret < 0 ? ret : data | ret;

}



static int w5100_spi_write16(struct net_device *ndev, u16 addr, u16 data)

{

	int ret;



	ret = w5100_spi_write(ndev, addr, data >> 8);

	if (ret)

		return ret;



	return w5100_spi_write(ndev, addr + 1, data & 0xff);

}



static int w5100_spi_readbulk(struct net_device *ndev, u16 addr, u8 *buf,

			      int len)

{

	int i;



	for (i = 0; i < len; i++) {

		int ret = w5100_spi_read(ndev, addr + i);



		if (ret < 0)

			return ret;

		buf[i] = ret;

	}



	return 0;

}



static int w5100_spi_writebulk(struct net_device *ndev, u16 addr, const u8 *buf,

			       int len)

{

	int i;



	for (i = 0; i < len; i++) {

		int ret = w5100_spi_write(ndev, addr + i, buf[i]);



		if (ret)

			return ret;

	}



	return 0;

}



static const struct w5100_ops w5100_spi_ops = {

	.may_sleep = true,

	.chip_id = W5100,

	.read = w5100_spi_read,

	.write = w5100_spi_write,

	.read16 = w5100_spi_read16,

	.write16 = w5100_spi_write16,

	.readbulk = w5100_spi_readbulk,

	.writebulk = w5100_spi_writebulk,

};



#define W5200_SPI_WRITE_OPCODE 0x80



struct w5200_spi_priv {

	/* Serialize access to cmd_buf */

	struct mutex cmd_lock;



	/* DMA (thus cache coherency maintenance) requires the

	 * transfer buffers to live in their own cache lines.

	 */

	u8 cmd_buf[4] ____cacheline_aligned;

};



static struct w5200_spi_priv *w5200_spi_priv(struct net_device *ndev)

{

	return w5100_ops_priv(ndev);

}



static int w5200_spi_init(struct net_device *ndev)

{

	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);



	mutex_init(&spi_priv->cmd_lock);



	return 0;

}



static int w5200_spi_read(struct net_device *ndev, u16 addr)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 1 };

	u8 data;

	int ret;



	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, 1);



	return ret ? ret : data;

}



static int w5200_spi_write(struct net_device *ndev, u16 addr, u8 data)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[5] = { addr >> 8, addr & 0xff, W5200_SPI_WRITE_OPCODE, 1, data };



	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);

}



static int w5200_spi_read16(struct net_device *ndev, u16 addr)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[4] = { addr >> 8, addr & 0xff, 0, 2 };

	__be16 data;

	int ret;



	ret = spi_write_then_read(spi, cmd, sizeof(cmd), &data, sizeof(data));



	return ret ? ret : be16_to_cpu(data);

}



static int w5200_spi_write16(struct net_device *ndev, u16 addr, u16 data)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	u8 cmd[6] = {

		addr >> 8, addr & 0xff,

		W5200_SPI_WRITE_OPCODE, 2,

		data >> 8, data & 0xff

	};



	return spi_write_then_read(spi, cmd, sizeof(cmd), NULL, 0);

}



static int w5200_spi_readbulk(struct net_device *ndev, u16 addr, u8 *buf,

			      int len)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);

	struct spi_transfer xfer[] = {

		{

			.tx_buf = spi_priv->cmd_buf,

			.len = sizeof(spi_priv->cmd_buf),

		},

		{

			.rx_buf = buf,

			.len = len,

		},

	};

	int ret;



	mutex_lock(&spi_priv->cmd_lock);



	spi_priv->cmd_buf[0] = addr >> 8;

	spi_priv->cmd_buf[1] = addr;

	spi_priv->cmd_buf[2] = len >> 8;

	spi_priv->cmd_buf[3] = len;

	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));



	mutex_unlock(&spi_priv->cmd_lock);



	return ret;

}



static int w5200_spi_writebulk(struct net_device *ndev, u16 addr, const u8 *buf,

			       int len)

{

	struct spi_device *spi = to_spi_device(ndev->dev.parent);

	struct w5200_spi_priv *spi_priv = w5200_spi_priv(ndev);

	struct spi_transfer xfer[] = {

		{

			.tx_buf = spi_priv->cmd_buf,

			.len = sizeof(spi_priv->cmd_buf),

		},

		{

			.tx_buf = buf,

			.len = len,

		},

	};

	int ret;



	mutex_lock(&spi_priv->cmd_lock);



	spi_priv->cmd_buf[0] = addr >> 8;

	spi_priv->cmd_buf[1] = addr;

	spi_priv->cmd_buf[2] = W5200_SPI_WRITE_OPCODE | (len >> 8);

	spi_priv->cmd_buf[3] = len;

	ret = spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));



	mutex_unlock(&spi_priv->cmd_lock);



	return ret;

}



static const struct w5100_ops w5200_ops = {

	.may_sleep = true,

	.chip_id = W5200,

	.read = w5200_spi_read,

	.write = w5200_spi_write,

	.read16 = w5200_spi_read16,

	.write16 = w5200_spi_write16,

	.readbulk = w5200_spi_readbulk,

	.writebulk = w5200_spi_writebulk,

	.init = w5200_spi_init,

};



static int w5100_spi_probe(struct spi_device *spi)

{

	const struct spi_device_id *id = spi_get_device_id(spi);

	const struct w5100_ops *ops;

	int priv_size;



	switch (id->driver_data) {

	case W5100:

		ops = &w5100_spi_ops;

		priv_size = 0;

		break;

	case W5200:

		ops = &w5200_ops;

		priv_size = sizeof(struct w5200_spi_priv);

		break;

	default:

		return -EINVAL;

	}



	return w5100_probe(&spi->dev, ops, priv_size, NULL, spi->irq, -EINVAL);

}



static int w5100_spi_remove(struct spi_device *spi)

{

	return w5100_remove(&spi->dev);

}



static const struct spi_device_id w5100_spi_ids[] = {

	{ "w5100", W5100 },

	{ "w5200", W5200 },

	{}

};

MODULE_DEVICE_TABLE(spi, w5100_spi_ids);



static struct spi_driver w5100_spi_driver = {

	.driver		= {

		.name	= "w5100",

		.pm	= &w5100_pm_ops,

	},

	.probe		= w5100_spi_probe,

	.remove		= w5100_spi_remove,

	.id_table	= w5100_spi_ids,

};

module_spi_driver(w5100_spi_driver);



MODULE_DESCRIPTION("WIZnet W5100/W5200 Ethernet driver for SPI mode");

MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");

MODULE_LICENSE("GPL");

drivers/net/ethernet/wiznet/w5100.c

+654 −281

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/wiznet/w5100.h

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Original line number Diff line number Diff line 
/*

 * Ethernet driver for the WIZnet W5100 chip.

 *

 * Copyright (C) 2006-2008 WIZnet Co.,Ltd.

 * Copyright (C) 2012 Mike Sinkovsky <msink@permonline.ru>

 *

 * Licensed under the GPL-2 or later.

 */



enum {

	W5100,

	W5200,

};



struct w5100_ops {

	bool may_sleep;

	int chip_id;

	int (*read)(struct net_device *ndev, u16 addr);

	int (*write)(struct net_device *ndev, u16 addr, u8 data);

	int (*read16)(struct net_device *ndev, u16 addr);

	int (*write16)(struct net_device *ndev, u16 addr, u16 data);

	int (*readbulk)(struct net_device *ndev, u16 addr, u8 *buf, int len);

	int (*writebulk)(struct net_device *ndev, u16 addr, const u8 *buf,

			 int len);

	int (*reset)(struct net_device *ndev);

	int (*init)(struct net_device *ndev);

};



void *w5100_ops_priv(const struct net_device *ndev);



int w5100_probe(struct device *dev, const struct w5100_ops *ops,

		int sizeof_ops_priv, u8 *mac_addr, int irq, int link_gpio);

int w5100_remove(struct device *dev);



extern const struct dev_pm_ops w5100_pm_ops;