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Commit ec69b269 authored by Yuriy Kolerov's avatar Yuriy Kolerov Committed by Vineet Gupta
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ARCv2: IDU-intc: Delete deprecated parameters in Device Trees 



No need for specifying a list of interrupts in the declaration
of IDU interrupt controller anymore since the kernel can obtain
a number of supported interrupts from the build register.

Also delete support of the second parameter for devices which
are connected to IDU because it is not used anywhere.

Signed-off-by: default avatarYuriy Kolerov <yuriy.kolerov@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent fc73965e

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

+6 −18
Original line number Diff line number Diff line
@@ -8,15 +8,11 @@ Properties: 
- compatible: "snps,archs-idu-intc"

- interrupt-controller: This is an interrupt controller.

- interrupt-parent: <reference to parent core intc>

- #interrupt-cells: Must be <2>.

- interrupts: <...> specifies the upstream core irqs

- #interrupt-cells: Must be <1>.



  First cell specifies the "common" IRQ from peripheral to IDU

  Second cell specifies the irq distribution mode to cores

     0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3



  The second cell in interrupts property is deprecated and may be ignored by

  the kernel.

  Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N

  of the particular interrupt line of IDU corresponds to the line N+24 of the

  core interrupt controller.



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.
@@ -32,18 +28,10 @@ Example: 
		compatible = "snps,archs-idu-intc";

		interrupt-controller;

		interrupt-parent = <&core_intc>;



		/*

		 * <hwirq  distribution>

		 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

		 */

		#interrupt-cells = <2>;



		/* upstream core irqs: downstream these are "COMMON" irq 0,1..  */

		interrupts = <24 25 26 27 28 29 30 31>;

		#interrupt-cells = <1>;

	};



	some_device: serial@c0fc1000 {

		interrupt-parent = <&idu_intc>;

		interrupts = <0 0>;	/* upstream idu IRQ #24, Round Robin */

		interrupts = <0>;	/* upstream idu IRQ #24 */

	};

arch/arc/boot/dts/axc003_idu.dtsi

+3 −20
Original line number Diff line number Diff line
@@ -40,18 +40,7 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25>;

			#interrupt-cells = <1>;

		};



		/*
@@ -73,12 +62,7 @@ 
				interrupt-controller;

				#interrupt-cells = <2>;

				interrupt-parent = <&idu_intc>;



				/*

				 * cmn irq 1 -> cpu irq 25

				 * Distribute to cpu0 only

				 */

				interrupts = <1 1>;

				interrupts = <1>;

			};

		};
@@ -119,8 +103,7 @@ 
		reg = < 0xe0012000 0x200 >;

		interrupt-controller;

		interrupt-parent = <&idu_intc>;

		interrupts = <0 1>;	/* cmn irq 0 -> cpu irq 24

					   distribute to cpu0 only */

		interrupts = <0>;

	};



	memory {

arch/arc/boot/dts/haps_hs_idu.dts

+2 −8
Original line number Diff line number Diff line
@@ -54,11 +54,7 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;

			/* <hwirq  distribution>

			distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3 */

			#interrupt-cells = <2>;

			interrupts = <24 25 26 27 28 29 30 31>;



			#interrupt-cells = <1>;

		};



		uart0: serial@f0000000 {
@@ -66,9 +62,7 @@ 
			compatible = "ns16550a";

			reg = <0xf0000000 0x2000>;

			interrupt-parent = <&idu_intc>;

			/* interrupts = <0 1>;  DEST=1*/

			/* interrupts = <0 2>;  DEST=2*/

			interrupts = <0 0>;  /* RR*/

			interrupts = <0>;

			clock-frequency = <50000000>;

			baud = <115200>;

			reg-shift = <2>;

arch/arc/boot/dts/nsim_hs_idu.dts

+2 −13
Original line number Diff line number Diff line
@@ -46,25 +46,14 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25 26 27 28 29 30 31>;

			#interrupt-cells = <1>;

		};



		arcuart0: serial@c0fc1000 {

			compatible = "snps,arc-uart";

			reg = <0xc0fc1000 0x100>;

			interrupt-parent = <&idu_intc>;

			interrupts = <0 0>;

			interrupts = <0>;

			clock-frequency = <80000000>;

			current-speed = <115200>;

			status = "okay";

arch/arc/boot/dts/nsimosci_hs_idu.dts

+4 −16
Original line number Diff line number Diff line
@@ -50,26 +50,14 @@ 
			compatible = "snps,archs-idu-intc";

			interrupt-controller;

			interrupt-parent = <&core_intc>;



			/*

			 * <hwirq  distribution>

			 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3

			 */

			#interrupt-cells = <2>;



			/*

			 * upstream irqs to core intc - downstream these are

			 * "COMMON" irq 0,1..

			 */

			interrupts = <24 25 26 27 28 29 30 31>;

			#interrupt-cells = <1>;

		};



		uart0: serial@f0000000 {

			compatible = "ns8250";

			reg = <0xf0000000 0x2000>;

			interrupt-parent = <&idu_intc>;

			interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24

						RR distribute to all cpus */

			interrupts = <0>;

			clock-frequency = <3686400>;

			baud = <115200>;

			reg-shift = <2>;
@@ -93,7 +81,7 @@ 
		ps2: ps2@f9001000 {

			compatible = "snps,arc_ps2";

			reg = <0xf9000400 0x14>;

			interrupts = <3 0>;

			interrupts = <3>;

			interrupt-parent = <&idu_intc>;

			interrupt-names = "arc_ps2_irq";

		};
@@ -102,7 +90,7 @@ 
			compatible = "ezchip,nps-mgt-enet";

			reg = <0xf0003000 0x44>;

			interrupt-parent = <&idu_intc>;

			interrupts = <1 2>;

			interrupts = <1>;

		};



		arcpct0: pct {