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Commit ec38f188 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: add bypass mode for vce3.0 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarEric Huang <JinhuiEric.Huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a93d54d8

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

+15 −0
Original line number Original line Diff line number Diff line
@@ -655,6 +655,18 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, 
	return 0;

	return 0;

}

}





static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool enable)

{

	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);



	if (enable)

		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;

	else

		tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;



	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);

}



static int vce_v3_0_set_clockgating_state(void *handle,

static int vce_v3_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

					  enum amd_clockgating_state state)

{

{
@@ -662,6 +674,9 @@ static int vce_v3_0_set_clockgating_state(void *handle, 
	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;

	int i;

	int i;





	if (adev->asic_type == CHIP_POLARIS10)

		vce_v3_set_bypass_mode(adev, enable);



	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))

	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))

		return 0;

		return 0;