Loading qcom/lagoon-sde-pll.dtsi +0 −16 Original line number Diff line number Diff line Loading @@ -45,8 +45,6 @@ reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; gdsc-supply = <&mdss_core_gdsc>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, Loading @@ -54,20 +52,6 @@ clock-names = "iface_clk", "ref_clk_src", "ref_clk", "pipe_clk"; clock-rate = <0>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; }; Loading
qcom/lagoon-sde-pll.dtsi +0 −16 Original line number Diff line number Diff line Loading @@ -45,8 +45,6 @@ reg-names = "pll_base", "phy_base", "ln_tx0_base", "ln_tx1_base", "gdsc_base"; gdsc-supply = <&mdss_core_gdsc>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, Loading @@ -54,20 +52,6 @@ clock-names = "iface_clk", "ref_clk_src", "ref_clk", "pipe_clk"; clock-rate = <0>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; }; };