Merge "msm: kgsl: Set UBWC correctly for DDR 4 and 5" (ebc7d738) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/msm/adreno.c

+1 −3

Original line number	Diff line number	Diff line
		@@ -2485,9 +2485,7 @@ static int adreno_prop_u32(struct kgsl_device *device,
		u32 val = 0;

		if (param->type == KGSL_PROP_HIGHEST_BANK_BIT) {
		if (of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &val))
		return -EINVAL;
		val = adreno_dev->highest_bank_bit;
		} else if (param->type == KGSL_PROP_MIN_ACCESS_LENGTH)
		of_property_read_u32(device->pdev->dev.of_node,
		"qcom,min-access-length", &val);

drivers/gpu/msm/adreno.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -443,6 +443,7 @@ enum gpu_coresight_sources {
		* @lm_threshold_cross: number of current peaks exceeding threshold
		* @ifpc_count: Number of times the GPU went into IFPC
		* @speed_bin: Indicate which power level set to use
		* @highest_bank_bit: Value of the highest bank bit
		* @csdev: Pointer to a coresight device (if applicable)
		* @gpmu_throttle_counters - counteers for number of throttled clocks
		* @irq_storm_work: Worker to handle possible interrupt storms
		@@ -517,6 +518,7 @@ struct adreno_device {
		uint32_t ifpc_count;

		unsigned int speed_bin;
		unsigned int highest_bank_bit;
		unsigned int quirks;

		struct coresight_device *csdev[GPU_CORESIGHT_MAX];

drivers/gpu/msm/adreno_a5xx.c

+25 −21

Original line number	Diff line number	Diff line
		@@ -256,6 +256,18 @@ static int a5xx_critical_packet_construct(struct adreno_device *adreno_dev)

		static void a5xx_init(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

		of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &adreno_dev->highest_bank_bit);

		if (WARN(adreno_dev->highest_bank_bit < 13 \|\|
		adreno_dev->highest_bank_bit > 16,
		"The highest-bank-bit property is invalid\n"))
		adreno_dev->highest_bank_bit =
		clamp_t(unsigned int, adreno_dev->highest_bank_bit,
		13, 16);

		if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
		INIT_WORK(&adreno_dev->gpmu_work, a5xx_gpmu_reset);

		@@ -1599,11 +1611,8 @@ static void a5xx_start(struct adreno_device *adreno_dev)
		}

		kgsl_regwrite(device, A5XX_RBBM_AHB_CNTL2, 0x0000003F);

		if (!of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &bit)) {
		if (bit >= 13 && bit <= 16) {
		bit = (bit - 13) & 0x03;
		bit = adreno_dev->highest_bank_bit ?
		(adreno_dev->highest_bank_bit - 13) & 0x03 : 0;

		/*
		* Program the highest DDR bank bit that was passed in
		@@ -1615,13 +1624,8 @@ static void a5xx_start(struct adreno_device *adreno_dev)

		kgsl_regwrite(device, A5XX_TPL1_MODE_CNTL, bit << 7);
		kgsl_regwrite(device, A5XX_RB_MODE_CNTL, bit << 1);
		if (adreno_is_a540(adreno_dev) \|\|
		adreno_is_a512(adreno_dev))
		kgsl_regwrite(device, A5XX_UCHE_DBG_ECO_CNTL_2,
		bit);
		}

		}
		if (adreno_is_a540(adreno_dev) \|\| adreno_is_a512(adreno_dev))
		kgsl_regwrite(device, A5XX_UCHE_DBG_ECO_CNTL_2, bit);

		/* Disable All flat shading optimization */
		kgsl_regrmw(device, A5XX_VPC_DBG_ECO_CNTL, 0, 0x1 << 10);

drivers/gpu/msm/adreno_a6xx.c

+22 −17

Original line number	Diff line number	Diff line
		@@ -5,6 +5,7 @@

		#include <linux/firmware.h>
		#include <linux/of.h>
		#include <linux/of_fdt.h>
		#include <soc/qcom/subsystem_restart.h>

		#include "adreno.h"
		@@ -15,10 +16,6 @@
		#include "kgsl_gmu.h"
		#include "kgsl_trace.h"

		#define MIN_HBB 13
		#define HBB_LOWER_MASK 0x3
		#define HBB_UPPER_SHIFT 0x2

		static struct a6xx_protected_regs {
		unsigned int base;
		unsigned int count;
		@@ -166,6 +163,23 @@ static void a6xx_pwrup_reglist_init(struct adreno_device *adreno_dev)

		static void a6xx_init(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

		adreno_dev->highest_bank_bit = 13;
		of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &adreno_dev->highest_bank_bit);

		if (WARN(adreno_dev->highest_bank_bit < 13 \|\|
		adreno_dev->highest_bank_bit > 16,
		"The highest-bank-bit property is invalid\n"))
		adreno_dev->highest_bank_bit =
		clamp_t(unsigned int, adreno_dev->highest_bank_bit,
		13, 16);

		/* LP DDR4 highest bank bit is different and needs to be overridden */
		if (adreno_is_a650(adreno_dev) && of_fdt_get_ddrtype() == 0x7)
		adreno_dev->highest_bank_bit = 15;

		a6xx_crashdump_init(adreno_dev);

		/*
		@@ -536,10 +550,6 @@ static void a6xx_start(struct adreno_device *adreno_dev)
		kgsl_regwrite(device, A6XX_RBBM_INT_2_MASK, 0x00000010);
		}

		if (of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &bit))
		bit = MIN_HBB;

		if (of_property_read_u32(device->pdev->dev.of_node,
		"qcom,min-access-length", &mal))
		mal = 32;
		@@ -568,15 +578,10 @@ static void a6xx_start(struct adreno_device *adreno_dev)
		break;
		}

		if (bit >= 13 && bit <= 17) {
		bit = bit - MIN_HBB;
		lower_bit = bit & HBB_LOWER_MASK;
		upper_bit = (bit >> HBB_UPPER_SHIFT) & 1;
		} else {
		lower_bit = 0;
		upper_bit = 0;
		}

		bit = adreno_dev->highest_bank_bit ?
		adreno_dev->highest_bank_bit - 13 : 0;
		lower_bit = bit & 0x3;
		upper_bit = (bit >> 0x2) & 1;
		mal = (mal == 64) ? 1 : 0;

		uavflagprd_inv = (adreno_is_a650_family(adreno_dev)) ? 2 : 0;