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Commit ebc348b2 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Move semaphore specific ring members to struct 



This will be helpful in abstracting some of the code in preparation for
gen8 semaphores.

v2: Move mbox stuff to a separate struct

v3: Rebased over VCS2 work

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0d116a29

drivers/gpu/drm/i915/i915_gem.c

+5 −5
Original line number Diff line number Diff line
@@ -2119,8 +2119,8 @@ i915_gem_init_seqno(struct drm_device *dev, u32 seqno) 
	for_each_ring(ring, dev_priv, i) {

		intel_ring_init_seqno(ring, seqno);



		for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)

			ring->sync_seqno[j] = 0;

		for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)

			ring->semaphore.sync_seqno[j] = 0;

	}



	return 0;
@@ -2692,7 +2692,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, 
	idx = intel_ring_sync_index(from, to);



	seqno = obj->last_read_seqno;

	if (seqno <= from->sync_seqno[idx])

	if (seqno <= from->semaphore.sync_seqno[idx])

		return 0;



	ret = i915_gem_check_olr(obj->ring, seqno);
@@ -2700,13 +2700,13 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, 
		return ret;



	trace_i915_gem_ring_sync_to(from, to, seqno);

	ret = to->sync_to(to, from, seqno);

	ret = to->semaphore.sync_to(to, from, seqno);

	if (!ret)

		/* We use last_read_seqno because sync_to()

		 * might have just caused seqno wrap under

		 * the radar.

		 */

		from->sync_seqno[idx] = obj->last_read_seqno;

		from->semaphore.sync_seqno[idx] = obj->last_read_seqno;



	return ret;

}

drivers/gpu/drm/i915/i915_gpu_error.c

+3 −3
Original line number Diff line number Diff line
@@ -757,14 +757,14 @@ static void i915_record_ring_state(struct drm_device *dev, 
			= I915_READ(RING_SYNC_0(ring->mmio_base));

		ering->semaphore_mboxes[1]

			= I915_READ(RING_SYNC_1(ring->mmio_base));

		ering->semaphore_seqno[0] = ring->sync_seqno[0];

		ering->semaphore_seqno[1] = ring->sync_seqno[1];

		ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];

		ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];

	}



	if (HAS_VEBOX(dev)) {

		ering->semaphore_mboxes[2] =

			I915_READ(RING_SYNC_2(ring->mmio_base));

		ering->semaphore_seqno[2] = ring->sync_seqno[2];

		ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];

	}



	if (INTEL_INFO(dev)->gen >= 4) {

drivers/gpu/drm/i915/i915_irq.c

+1 −2
Original line number Diff line number Diff line
@@ -2582,8 +2582,7 @@ semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr) 
			if(ring == signaller)

				continue;



			if (sync_bits ==

			    signaller->semaphore_register[ring->id])

			if (sync_bits == signaller->semaphore.mbox.wait[ring->id])

				return signaller;

		}

	}

drivers/gpu/drm/i915/intel_ringbuffer.c

+61 −63
Original line number Diff line number Diff line
@@ -706,7 +706,7 @@ gen6_add_request(struct intel_ring_buffer *ring) 


	if (i915_semaphore_is_enabled(dev)) {

		for_each_ring(useless, dev_priv, i) {

			u32 mbox_reg = ring->signal_mbox[i];

			u32 mbox_reg = ring->semaphore.mbox.signal[i];

			if (mbox_reg != GEN6_NOSYNC)

				update_mboxes(ring, mbox_reg);

		}
@@ -740,10 +740,11 @@ gen6_ring_sync(struct intel_ring_buffer *waiter, 
	       struct intel_ring_buffer *signaller,

	       u32 seqno)

{

	int ret;

	u32 dw1 = MI_SEMAPHORE_MBOX |

		  MI_SEMAPHORE_COMPARE |

		  MI_SEMAPHORE_REGISTER;

	u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];

	int ret;



	/* Throughout all of the GEM code, seqno passed implies our current

	 * seqno is >= the last seqno executed. However for hardware the
@@ -751,8 +752,7 @@ gen6_ring_sync(struct intel_ring_buffer *waiter, 
	 */

	seqno -= 1;



	WARN_ON(signaller->semaphore_register[waiter->id] ==

		MI_SEMAPHORE_SYNC_INVALID);

	WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);



	ret = intel_ring_begin(waiter, 4);

	if (ret)
@@ -760,9 +760,7 @@ gen6_ring_sync(struct intel_ring_buffer *waiter, 


	/* If seqno wrap happened, omit the wait with no-ops */

	if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {

		intel_ring_emit(waiter,

				dw1 |

				signaller->semaphore_register[waiter->id]);

		intel_ring_emit(waiter, dw1 | wait_mbox);

		intel_ring_emit(waiter, seqno);

		intel_ring_emit(waiter, 0);

		intel_ring_emit(waiter, MI_NOOP);
@@ -1414,7 +1412,7 @@ static int intel_init_ring_buffer(struct drm_device *dev, 
	INIT_LIST_HEAD(&ring->active_list);

	INIT_LIST_HEAD(&ring->request_list);

	ring->size = 32 * PAGE_SIZE;

	memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));

	memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));



	init_waitqueue_head(&ring->irq_queue);
@@ -1921,23 +1919,23 @@ int intel_init_render_ring_buffer(struct drm_device *dev) 
		ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;

		ring->get_seqno = gen6_ring_get_seqno;

		ring->set_seqno = ring_set_seqno;

		ring->sync_to = gen6_ring_sync;

		ring->semaphore.sync_to = gen6_ring_sync;

		/*

		 * The current semaphore is only applied on pre-gen8 platform.

		 * And there is no VCS2 ring on the pre-gen8 platform. So the

		 * semaphore between RCS and VCS2 is initialized as INVALID.

		 * Gen8 will initialize the sema between VCS2 and RCS later.

		 */

		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;

		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;

		ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;

		ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

		ring->signal_mbox[RCS] = GEN6_NOSYNC;

		ring->signal_mbox[VCS] = GEN6_VRSYNC;

		ring->signal_mbox[BCS] = GEN6_BRSYNC;

		ring->signal_mbox[VECS] = GEN6_VERSYNC;

		ring->signal_mbox[VCS2] = GEN6_NOSYNC;

		ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;

		ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;

		ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;

		ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;

		ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;

		ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;

		ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;

		ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;

	} else if (IS_GEN5(dev)) {

		ring->add_request = pc_render_add_request;

		ring->flush = gen4_render_ring_flush;
@@ -2105,23 +2103,23 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) 
			ring->dispatch_execbuffer =

				gen6_ring_dispatch_execbuffer;

		}

		ring->sync_to = gen6_ring_sync;

		ring->semaphore.sync_to = gen6_ring_sync;

		/*

		 * The current semaphore is only applied on pre-gen8 platform.

		 * And there is no VCS2 ring on the pre-gen8 platform. So the

		 * semaphore between VCS and VCS2 is initialized as INVALID.

		 * Gen8 will initialize the sema between VCS2 and VCS later.

		 */

		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;

		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;

		ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;

		ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

		ring->signal_mbox[RCS] = GEN6_RVSYNC;

		ring->signal_mbox[VCS] = GEN6_NOSYNC;

		ring->signal_mbox[BCS] = GEN6_BVSYNC;

		ring->signal_mbox[VECS] = GEN6_VEVSYNC;

		ring->signal_mbox[VCS2] = GEN6_NOSYNC;

		ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;

		ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;

		ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;

		ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

		ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;

		ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;

		ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;

		ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;

		ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;

	} else {

		ring->mmio_base = BSD_RING_BASE;

		ring->flush = bsd_ring_flush;
@@ -2173,23 +2171,23 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) 
	ring->irq_put = gen8_ring_put_irq;

	ring->dispatch_execbuffer =

			gen8_ring_dispatch_execbuffer;

	ring->sync_to = gen6_ring_sync;

	ring->semaphore.sync_to = gen6_ring_sync;

	/*

	 * The current semaphore is only applied on the pre-gen8. And there

	 * is no bsd2 ring on the pre-gen8. So now the semaphore_register

	 * between VCS2 and other ring is initialized as invalid.

	 * Gen8 will initialize the sema between VCS2 and other ring later.

	 */

	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->signal_mbox[RCS] = GEN6_NOSYNC;

	ring->signal_mbox[VCS] = GEN6_NOSYNC;

	ring->signal_mbox[BCS] = GEN6_NOSYNC;

	ring->signal_mbox[VECS] = GEN6_NOSYNC;

	ring->signal_mbox[VCS2] = GEN6_NOSYNC;

	ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;



	ring->init = init_ring_common;
@@ -2222,23 +2220,23 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) 
		ring->irq_put = gen6_ring_put_irq;

		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;

	}

	ring->sync_to = gen6_ring_sync;

	ring->semaphore.sync_to = gen6_ring_sync;

	/*

	 * The current semaphore is only applied on pre-gen8 platform. And

	 * there is no VCS2 ring on the pre-gen8 platform. So the semaphore

	 * between BCS and VCS2 is initialized as INVALID.

	 * Gen8 will initialize the sema between BCS and VCS2 later.

	 */

	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;

	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;

	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;

	ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->signal_mbox[RCS] = GEN6_RBSYNC;

	ring->signal_mbox[VCS] = GEN6_VBSYNC;

	ring->signal_mbox[BCS] = GEN6_NOSYNC;

	ring->signal_mbox[VECS] = GEN6_VEBSYNC;

	ring->signal_mbox[VCS2] = GEN6_NOSYNC;

	ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;

	ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;

	ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;

	ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;

	ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;

	ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;

	ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;

	ring->init = init_ring_common;



	return intel_init_ring_buffer(dev, ring);
@@ -2271,17 +2269,17 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) 
		ring->irq_put = hsw_vebox_put_irq;

		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;

	}

	ring->sync_to = gen6_ring_sync;

	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;

	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;

	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;

	ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore_register[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->signal_mbox[RCS] = GEN6_RVESYNC;

	ring->signal_mbox[VCS] = GEN6_VVESYNC;

	ring->signal_mbox[BCS] = GEN6_BVESYNC;

	ring->signal_mbox[VECS] = GEN6_NOSYNC;

	ring->signal_mbox[VCS2] = GEN6_NOSYNC;

	ring->semaphore.sync_to = gen6_ring_sync;

	ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;

	ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;

	ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;

	ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;

	ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;

	ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;

	ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;

	ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;

	ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;

	ring->init = init_ring_common;



	return intel_init_ring_buffer(dev, ring);

drivers/gpu/drm/i915/intel_ringbuffer.h

+12 −7
Original line number Diff line number Diff line
@@ -90,7 +90,6 @@ struct intel_ring_buffer { 
	unsigned irq_refcount; /* protected by dev_priv->irq_lock */

	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */

	u32		trace_irq_seqno;

	u32		sync_seqno[I915_NUM_RINGS-1];

	bool __must_check (*irq_get)(struct intel_ring_buffer *ring);

	void		(*irq_put)(struct intel_ring_buffer *ring);
@@ -118,14 +117,20 @@ struct intel_ring_buffer { 
#define I915_DISPATCH_SECURE 0x1

#define I915_DISPATCH_PINNED 0x2

	void		(*cleanup)(struct intel_ring_buffer *ring);



	struct {

		u32	sync_seqno[I915_NUM_RINGS-1];

		/* AKA wait() */

		int	(*sync_to)(struct intel_ring_buffer *ring,

				   struct intel_ring_buffer *to,

				   u32 seqno);



		struct {

			/* our mbox written by others */

	u32		semaphore_register[I915_NUM_RINGS];

			u32		wait[I915_NUM_RINGS];

			/* mboxes this ring signals to */

	u32		signal_mbox[I915_NUM_RINGS];

			u32		signal[I915_NUM_RINGS];

		} mbox;

	} semaphore;



	/**

	 * List of objects currently involved in rendering from the