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Commit ebb6cc03 authored by Yan, Zheng's avatar Yan, Zheng Committed by Thomas Gleixner
Browse files

perf/x86: Fixes for Nehalem-EX uncore driver 



This patch includes following fixes and update:
 - Only some events in the Sbox and Mbox can use the match/mask
   registers, add code to check this.
 - The format definitions for xbr_mm_cfg and xbr_match registers
   in the Rbox are wrong, xbr_mm_cfg should use 32 bits, xbr_match
   should use 64 bits.
 - Cleanup the Rbox code. Compute the addresses extra registers in
   the enable_event function instead of the hw_config function.
   This simplifies the code in nhmex_rbox_alter_er().

Signed-off-by: default avatarYan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1344229882-3907-2-git-send-email-zheng.z.yan@intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent cffa59ba

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+86 −109
Original line number Diff line number Diff line
@@ -796,7 +796,6 @@ static struct intel_uncore_type *nhm_msr_uncores[] = { 


DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");

DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");

DEFINE_UNCORE_FORMAT_ATTR(mm_cfg, mm_cfg, "config:63");

DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");

DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
@@ -1032,24 +1031,22 @@ static struct intel_uncore_type nhmex_uncore_bbox = { 


static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)

{

	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;

	struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;

	struct hw_perf_event *hwc = &event->hw;

	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;

	struct hw_perf_event_extra *reg2 = &hwc->branch_reg;



	if (event->attr.config & NHMEX_S_PMON_MM_CFG_EN) {

		reg1->config = event->attr.config1;

		reg2->config = event->attr.config2;

	} else {

		reg1->config = ~0ULL;

		reg2->config = ~0ULL;

	}

	/* only TO_R_PROG_EV event uses the match/mask register */

	if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=

	    NHMEX_S_EVENT_TO_R_PROG_EV)

		return 0;



	if (box->pmu->pmu_idx == 0)

		reg1->reg = NHMEX_S0_MSR_MM_CFG;

	else

		reg1->reg = NHMEX_S1_MSR_MM_CFG;



	reg1->idx = 0;



	reg1->config = event->attr.config1;

	reg2->config = event->attr.config2;

	return 0;

}
@@ -1059,8 +1056,8 @@ static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct per 
	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;

	struct hw_perf_event_extra *reg2 = &hwc->branch_reg;



	if (reg1->idx != EXTRA_REG_NONE) {

		wrmsrl(reg1->reg, 0);

	if (reg1->config != ~0ULL || reg2->config != ~0ULL) {

		wrmsrl(reg1->reg + 1, reg1->config);

		wrmsrl(reg1->reg + 2, reg2->config);

		wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
@@ -1074,7 +1071,6 @@ static struct attribute *nhmex_uncore_sbox_formats_attr[] = { 
	&format_attr_edge.attr,

	&format_attr_inv.attr,

	&format_attr_thresh8.attr,

	&format_attr_mm_cfg.attr,

	&format_attr_match.attr,

	&format_attr_mask.attr,

	NULL,
@@ -1264,7 +1260,8 @@ nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event 
	}



	/* for the match/mask registers */

	if ((uncore_box_is_fake(box) || !reg2->alloc) &&

	if (reg2->idx != EXTRA_REG_NONE &&

	    (uncore_box_is_fake(box) || !reg2->alloc) &&

	    !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))

		goto fail;
@@ -1278,6 +1275,7 @@ nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event 
		if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))

			nhmex_mbox_alter_er(event, idx[0], true);

		reg1->alloc |= alloc;

		if (reg2->idx != EXTRA_REG_NONE)

			reg2->alloc = 1;

	}

	return NULL;
@@ -1342,9 +1340,6 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event 
	struct extra_reg *er;

	unsigned msr;

	int reg_idx = 0;



	if (WARN_ON_ONCE(reg1->idx != -1))

		return -EINVAL;

	/*

	 * The mbox events may require 2 extra MSRs at the most. But only

	 * the lower 32 bits in these MSRs are significant, so we can use
@@ -1355,11 +1350,6 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event 
			continue;

		if (event->attr.config1 & ~er->valid_mask)

			return -EINVAL;

		if (er->idx == __BITS_VALUE(reg1->idx, 0, 8) ||

		    er->idx == __BITS_VALUE(reg1->idx, 1, 8))

			continue;

		if (WARN_ON_ONCE(reg_idx >= 2))

			return -EINVAL;



		msr = er->msr + type->msr_offset * box->pmu->pmu_idx;

		if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
@@ -1368,6 +1358,8 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event 
		/* always use the 32~63 bits to pass the PLD config */

		if (er->idx == EXTRA_REG_NHMEX_M_PLD)

			reg_idx = 1;

		else if (WARN_ON_ONCE(reg_idx > 0))

			return -EINVAL;



		reg1->idx &= ~(0xff << (reg_idx * 8));

		reg1->reg &= ~(0xffff << (reg_idx * 16));
@@ -1376,7 +1368,11 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event 
		reg1->config = event->attr.config1;

		reg_idx++;

	}

	/* use config2 to pass the filter config */

	/*

	 * The mbox only provides ability to perform address matching

	 * for the PLD events.

	 */

	if (reg_idx == 2) {

		reg2->idx = EXTRA_REG_NHMEX_M_FILTER;

		if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)

			reg2->config = event->attr.config2;
@@ -1386,7 +1382,7 @@ static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event 
			reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;

		else

			reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;



	}

	return 0;

}
@@ -1422,6 +1418,7 @@ static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct per 
		wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),

			nhmex_mbox_shared_reg_config(box, idx));



	if (reg2->idx != EXTRA_REG_NONE) {

		wrmsrl(reg2->reg, 0);

		if (reg2->config != ~0ULL) {

			wrmsrl(reg2->reg + 1,
@@ -1430,6 +1427,7 @@ static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct per 
				(reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));

			wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);

		}

	}



	wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);

}
@@ -1440,7 +1438,7 @@ DEFINE_UNCORE_FORMAT_ATTR(wrap_mode, wrap_mode, "config:6"); 
DEFINE_UNCORE_FORMAT_ATTR(flag_mode,		flag_mode,	"config:7");

DEFINE_UNCORE_FORMAT_ATTR(inc_sel,		inc_sel,	"config:9-13");

DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel,		set_flag_sel,	"config:19-21");

DEFINE_UNCORE_FORMAT_ATTR(filter_cfg,	filter_cfg,	"config2:63");

DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en,	filter_cfg_en,	"config2:63");

DEFINE_UNCORE_FORMAT_ATTR(filter_match,		filter_match,	"config2:0-33");

DEFINE_UNCORE_FORMAT_ATTR(filter_mask,		filter_mask,	"config2:34-61");

DEFINE_UNCORE_FORMAT_ATTR(dsp,			dsp,		"config1:0-31");
@@ -1458,7 +1456,7 @@ static struct attribute *nhmex_uncore_mbox_formats_attr[] = { 
	&format_attr_flag_mode.attr,

	&format_attr_inc_sel.attr,

	&format_attr_set_flag_sel.attr,

	&format_attr_filter_cfg.attr,

	&format_attr_filter_cfg_en.attr,

	&format_attr_filter_match.attr,

	&format_attr_filter_mask.attr,

	&format_attr_dsp.attr,
@@ -1513,7 +1511,7 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event) 
	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;

	int port;



	/* adjust the main event selector */

	/* adjust the main event selector and extra register index */

	if (reg1->idx % 2) {

		reg1->idx--;

		hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
@@ -1522,29 +1520,17 @@ void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event) 
		hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;

	}



	/* adjust address or config of extra register */

	/* adjust extra register config */

	port = reg1->idx / 6 + box->pmu->pmu_idx * 4;

	switch (reg1->idx % 6) {

	case 0:

		reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);

		break;

	case 1:

		reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);

		break;

	case 2:

		/* the 8~15 bits to the 0~7 bits */

		/* shift the 8~15 bits to the 0~7 bits */

		reg1->config >>= 8;

		break;

	case 3:

		/* the 0~7 bits to the 8~15 bits */

		/* shift the 0~7 bits to the 8~15 bits */

		reg1->config <<= 8;

		break;

	case 4:

		reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);

		break;

	case 5:

		reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);

		break;

	};

}
@@ -1671,7 +1657,7 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event 
	struct hw_perf_event *hwc = &event->hw;

	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;

	struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;

	int port, idx;

	int idx;



	idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>

		NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
@@ -1681,27 +1667,11 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event 
	reg1->idx = idx;

	reg1->config = event->attr.config1;



	port = idx / 6 + box->pmu->pmu_idx * 4;

	idx %= 6;

	switch (idx) {

	case 0:

		reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG0(port);

		break;

	case 1:

		reg1->reg = NHMEX_R_MSR_PORTN_IPERF_CFG1(port);

		break;

	case 2:

	case 3:

		reg1->reg = NHMEX_R_MSR_PORTN_QLX_CFG(port);

		break;

	switch (idx % 6) {

	case 4:

	case 5:

		if (idx == 4)

			reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port);

		else

			reg1->reg = NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port);

		reg2->config = event->attr.config2;

		hwc->config |= event->attr.config & (~0ULL << 32);

		reg2->config = event->attr.config2;

		break;

	};

	return 0;
@@ -1727,28 +1697,34 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per 
	struct hw_perf_event *hwc = &event->hw;

	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;

	struct hw_perf_event_extra *reg2 = &hwc->branch_reg;

	int idx, er_idx;

	int idx, port;



	idx = reg1->idx % 6;

	er_idx = idx;

	if (er_idx > 2)

		er_idx--;

	er_idx += (reg1->idx / 6) * 5;

	idx = reg1->idx;

	port = idx / 6 + box->pmu->pmu_idx * 4;



	switch (idx) {

	switch (idx % 6) {

	case 0:

		wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);

		break;

	case 1:

		wrmsrl(reg1->reg, reg1->config);

		wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);

		break;

	case 2:

	case 3:

		wrmsrl(reg1->reg, nhmex_rbox_shared_reg_config(box, er_idx));

		wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),

			nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));

		break;

	case 4:

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),

			hwc->config >> 32);

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);

		break;

	case 5:

		wrmsrl(reg1->reg, reg1->config);

		wrmsrl(reg1->reg + 1, hwc->config >> 32);

		wrmsrl(reg1->reg + 2, reg2->config);

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),

			hwc->config >> 32);

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);

		wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);

		break;

	};
@@ -1756,8 +1732,8 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per 
		(hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));

}



DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config:32-63");

DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config1:0-63");

DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");

DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");

DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");

DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");

DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
@@ -2303,6 +2279,7 @@ int uncore_pmu_event_init(struct perf_event *event) 
	event->hw.idx = -1;

	event->hw.last_tag = ~0ULL;

	event->hw.extra_reg.idx = EXTRA_REG_NONE;

	event->hw.branch_reg.idx = EXTRA_REG_NONE;



	if (event->attr.config == UNCORE_FIXED_EVENT) {

		/* no fixed counter */

arch/x86/kernel/cpu/perf_event_intel_uncore.h

+1 −0
Original line number Diff line number Diff line
@@ -230,6 +230,7 @@ 
#define NHMEX_S1_MSR_MASK			0xe5a



#define NHMEX_S_PMON_MM_CFG_EN			(0x1ULL << 63)

#define NHMEX_S_EVENT_TO_R_PROG_EV		0



/* NHM-EX Mbox */

#define NHMEX_M0_MSR_GLOBAL_CTL			0xca0