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Commit eb64cad1 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Refactor gen6_set_rps 



What used to be a short-circuit now needs to adjust interrupt masking in
response to user requests for changing the min/max allowed frequencies.
This is currently done by a special case and early return, but the next
patch adds another common action to take, so refactor the code to reduce
duplication.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 037bde19

drivers/gpu/drm/i915/intel_pm.c

+14 −20
Original line number Diff line number Diff line
@@ -3017,15 +3017,10 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
	WARN_ON(val > dev_priv->rps.max_freq_softlimit);

	WARN_ON(val < dev_priv->rps.min_freq_softlimit);



	if (val == dev_priv->rps.cur_freq) {

	/* min/max delay may still have been modified so be sure to

		 * write the limits value */

		I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

			   gen6_rps_limits(dev_priv, val));



		return;

	}



	 * write the limits value.

	 */

	if (val != dev_priv->rps.cur_freq) {

		gen6_set_rps_thresholds(dev_priv, val);



		if (IS_HASWELL(dev))
@@ -3036,17 +3031,16 @@ void gen6_set_rps(struct drm_device *dev, u8 val) 
				   GEN6_FREQUENCY(val) |

				   GEN6_OFFSET(0) |

				   GEN6_AGGRESSIVE_TURBO);

	}



	/* Make sure we continue to get interrupts

	 * until we hit the minimum or maximum frequencies.

	 */

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,

		   gen6_rps_limits(dev_priv, val));

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));



	POSTING_READ(GEN6_RPNSWREQ);



	dev_priv->rps.cur_freq = val;



	trace_intel_gpu_freq_change(val * 50);

}