Loading qcom/lagoon.dtsi +18 −25 Original line number Diff line number Diff line Loading @@ -752,6 +752,23 @@ qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_QLINK_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; Loading Loading @@ -781,7 +798,7 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_QLINK_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; Loading Loading @@ -1003,10 +1020,6 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; #address-cells = <1>; #size-cells = <1>; ranges; system_pm { compatible = "qcom,system-pm"; }; Loading @@ -1020,26 +1033,6 @@ compatible = "qcom,lagoon-rpmh-clk"; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; qcom,rpmh-resource-name = "qphy.lvl"; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; }; disp_rsc: rsc@af20000 { Loading Loading
qcom/lagoon.dtsi +18 −25 Original line number Diff line number Diff line Loading @@ -752,6 +752,23 @@ qcom,instance-type = "ufs"; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_QLINK_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; Loading Loading @@ -781,7 +798,7 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_QLINK_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; Loading Loading @@ -1003,10 +1020,6 @@ <WAKE_TCS 3>, <CONTROL_TCS 1>; #address-cells = <1>; #size-cells = <1>; ranges; system_pm { compatible = "qcom,system-pm"; }; Loading @@ -1020,26 +1033,6 @@ compatible = "qcom,lagoon-rpmh-clk"; #clock-cells = <1>; }; ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; #phy-cells = <0>; ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <2>; qcom,rpmh-resource-name = "qphy.lvl"; clock-names = "ref_clk_src", "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; status = "disabled"; }; }; disp_rsc: rsc@af20000 { Loading