Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ead0cdc0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Vote for QLINK_CLK instead of XO_CLK"

parents 5601f547 a2a4894e
Loading
Loading
Loading
Loading
+18 −25
Original line number Diff line number Diff line
@@ -752,6 +752,23 @@
		qcom,instance-type = "ufs";
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;
		ufs-qcom-crypto = <&ufs_ice>;

		lanes-per-direction = <2>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&rpmhcc RPMH_QLINK_CLK>,
			<&gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
@@ -781,7 +798,7 @@
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_QLINK_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
@@ -1003,10 +1020,6 @@
				  <WAKE_TCS    3>,
				  <CONTROL_TCS 1>;

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		system_pm {
			compatible = "qcom,system-pm";
		};
@@ -1020,26 +1033,6 @@
			compatible = "qcom,lagoon-rpmh-clk";
			#clock-cells = <1>;
		};

		ufsphy_mem: ufsphy_mem@1d87000 {
			reg = <0x1d87000 0xe00>; /* PHY regs */
			reg-names = "phy_mem";
			#phy-cells = <0>;
			ufs-qcom-crypto = <&ufs_ice>;

			lanes-per-direction = <2>;

			qcom,rpmh-resource-name = "qphy.lvl";
			clock-names = "ref_clk_src",
				"ref_clk",
				"ref_aux_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_MEM_CLKREF_CLK>,
				<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

			status = "disabled";
		};

	};

	disp_rsc: rsc@af20000 {