fw-api: Fix compilation issue for tx monitor (eaca7918) · Commits · e / devices / android_kernel_oneplus_sm7250

hw/qcn9224/ack_report.h

0 → 100644

+94 −0

Original line number	Original line	Diff line number	Diff line

			/*
			* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
			*
			* Permission to use, copy, modify, and/or distribute this software for any
			* purpose with or without fee is hereby granted, provided that the above
			* copyright notice and this permission notice appear in all copies.
			*
			* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
			* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
			* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
			* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
			* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
			* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
			* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
			*/










			#ifndef _ACK_REPORT_H_
			#define _ACK_REPORT_H_
			#if !defined(__ASSEMBLER__)
			#endif

			#define NUM_OF_DWORDS_ACK_REPORT 1


			struct ack_report {
			#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
			uint32_t selfgen_response_reason : 4, // [3:0]
			ax_trigger_type : 4, // [7:4]
			sr_ppdu : 1, // [8:8]
			reserved : 7, // [15:9]
			frame_control : 16; // [31:16]
			#else
			uint32_t frame_control : 16, // [31:16]
			reserved : 7, // [15:9]
			sr_ppdu : 1, // [8:8]
			ax_trigger_type : 4, // [7:4]
			selfgen_response_reason : 4; // [3:0]
			#endif
			};




			#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
			#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
			#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
			#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f




			#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
			#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
			#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
			#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0




			#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
			#define ACK_REPORT_SR_PPDU_LSB 8
			#define ACK_REPORT_SR_PPDU_MSB 8
			#define ACK_REPORT_SR_PPDU_MASK 0x00000100




			#define ACK_REPORT_RESERVED_OFFSET 0x00000000
			#define ACK_REPORT_RESERVED_LSB 9
			#define ACK_REPORT_RESERVED_MSB 15
			#define ACK_REPORT_RESERVED_MASK 0x0000fe00




			#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
			#define ACK_REPORT_FRAME_CONTROL_LSB 16
			#define ACK_REPORT_FRAME_CONTROL_MSB 31
			#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000




			#endif

hw/qcn9224/eht_sig_usr_mu_mimo_info.h

0 → 100644

+154 −0

Original line number	Original line	Diff line number	Diff line

			/*
			* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
			*
			* Permission to use, copy, modify, and/or distribute this software for any
			* purpose with or without fee is hereby granted, provided that the above
			* copyright notice and this permission notice appear in all copies.
			*
			* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
			* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
			* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
			* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
			* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
			* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
			* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
			*/










			#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
			#define _EHT_SIG_USR_MU_MIMO_INFO_H_
			#if !defined(__ASSEMBLER__)
			#endif

			#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2


			struct eht_sig_usr_mu_mimo_info {
			#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
			uint32_t sta_id : 11, // [10:0]
			sta_mcs : 4, // [14:11]
			sta_coding : 1, // [15:15]
			sta_spatial_config : 6, // [21:16]
			reserved_0a : 1, // [22:22]
			rx_integrity_check_passed : 1, // [23:23]
			subband80_cc_mask : 8; // [31:24]
			uint32_t user_order_subband80_0 : 8, // [7:0]
			user_order_subband80_1 : 8, // [15:8]
			user_order_subband80_2 : 8, // [23:16]
			user_order_subband80_3 : 8; // [31:24]
			#else
			uint32_t subband80_cc_mask : 8, // [31:24]
			rx_integrity_check_passed : 1, // [23:23]
			reserved_0a : 1, // [22:22]
			sta_spatial_config : 6, // [21:16]
			sta_coding : 1, // [15:15]
			sta_mcs : 4, // [14:11]
			sta_id : 11; // [10:0]
			uint32_t user_order_subband80_3 : 8, // [31:24]
			user_order_subband80_2 : 8, // [23:16]
			user_order_subband80_1 : 8, // [15:8]
			user_order_subband80_0 : 8; // [7:0]
			#endif
			};




			#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff




			#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800




			#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000




			#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
			#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000




			#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
			#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
			#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000




			#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
			#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
			#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000




			#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
			#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
			#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
			#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000




			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff




			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00




			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000




			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
			#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000




			#endif

hw/qcn9224/eht_sig_usr_ofdma_info.h

0 → 100644

+174 −0

Original line number	Original line	Diff line number	Diff line

			/*
			* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
			*
			* Permission to use, copy, modify, and/or distribute this software for any
			* purpose with or without fee is hereby granted, provided that the above
			* copyright notice and this permission notice appear in all copies.
			*
			* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
			* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
			* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
			* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
			* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
			* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
			* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
			*/










			#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
			#define _EHT_SIG_USR_OFDMA_INFO_H_
			#if !defined(__ASSEMBLER__)
			#endif

			#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2


			struct eht_sig_usr_ofdma_info {
			#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
			uint32_t sta_id : 11, // [10:0]
			sta_mcs : 4, // [14:11]
			validate_0a : 1, // [15:15]
			nss : 4, // [19:16]
			txbf : 1, // [20:20]
			sta_coding : 1, // [21:21]
			reserved_0b : 1, // [22:22]
			rx_integrity_check_passed : 1, // [23:23]
			subband80_cc_mask : 8; // [31:24]
			uint32_t user_order_subband80_0 : 8, // [7:0]
			user_order_subband80_1 : 8, // [15:8]
			user_order_subband80_2 : 8, // [23:16]
			user_order_subband80_3 : 8; // [31:24]
			#else
			uint32_t subband80_cc_mask : 8, // [31:24]
			rx_integrity_check_passed : 1, // [23:23]
			reserved_0b : 1, // [22:22]
			sta_coding : 1, // [21:21]
			txbf : 1, // [20:20]
			nss : 4, // [19:16]
			validate_0a : 1, // [15:15]
			sta_mcs : 4, // [14:11]
			sta_id : 11; // [10:0]
			uint32_t user_order_subband80_3 : 8, // [31:24]
			user_order_subband80_2 : 8, // [23:16]
			user_order_subband80_1 : 8, // [15:8]
			user_order_subband80_0 : 8; // [7:0]
			#endif
			};




			#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
			#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
			#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff




			#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
			#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
			#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800




			#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
			#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
			#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000




			#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
			#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
			#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000




			#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
			#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
			#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000




			#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
			#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
			#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000




			#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
			#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
			#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000




			#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
			#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
			#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000




			#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
			#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
			#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
			#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000




			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff




			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00




			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000




			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
			#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000




			#endif

hw/qcn9224/eht_sig_usr_su_info.h

0 → 100644

+124 −0

Original line number	Original line	Diff line number	Diff line

			/*
			* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
			*
			* Permission to use, copy, modify, and/or distribute this software for any
			* purpose with or without fee is hereby granted, provided that the above
			* copyright notice and this permission notice appear in all copies.
			*
			* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
			* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
			* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
			* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
			* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
			* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
			* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
			*/










			#ifndef _EHT_SIG_USR_SU_INFO_H_
			#define _EHT_SIG_USR_SU_INFO_H_
			#if !defined(__ASSEMBLER__)
			#endif

			#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1


			struct eht_sig_usr_su_info {
			#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
			uint32_t sta_id : 11, // [10:0]
			sta_mcs : 4, // [14:11]
			validate_0a : 1, // [15:15]
			nss : 4, // [19:16]
			txbf : 1, // [20:20]
			sta_coding : 1, // [21:21]
			reserved_0b : 9, // [30:22]
			rx_integrity_check_passed : 1; // [31:31]
			#else
			uint32_t rx_integrity_check_passed : 1, // [31:31]
			reserved_0b : 9, // [30:22]
			sta_coding : 1, // [21:21]
			txbf : 1, // [20:20]
			nss : 4, // [19:16]
			validate_0a : 1, // [15:15]
			sta_mcs : 4, // [14:11]
			sta_id : 11; // [10:0]
			#endif
			};




			#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
			#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
			#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff




			#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
			#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
			#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800




			#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
			#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
			#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000




			#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
			#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
			#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000




			#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
			#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
			#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000




			#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
			#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
			#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000




			#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
			#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
			#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000




			#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
			#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
			#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
			#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000




			#endif

hw/qcn9224/he_sig_a_mu_ul_info.h

0 → 100644

+164 −0

File added.

Preview size limit exceeded, changes collapsed.