Commit ea589e9b authored Nov 30, 2014 by Lino Sanfilippo Committed by David S. Miller Dec 05, 2014

sky2: avoid pci write posting after disabling irqs



In sky2_change_mtu setting B0_IMSK to 0 may be delayed due to PCI write posting
which could result in irqs being still active when synchronize_irq is called.
Since we are not prepared to handle any further irqs after synchronize_irq
(our resources are freed after that) force the write by a consecutive read from
the same register.
Similar situation in sky2_all_down: Here we disabled irqs by a write to B0_IMSK
but did not ensure that this write took place before synchronize_irq. Fix that
too.

Signed-off-by: Lino Sanfilippo <LinoSanfilippo@gmx.de>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent 6276288a

drivers/net/ethernet/marvell/sky2.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -2419,6 +2419,7 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu)

		imask = sky2_read32(hw, B0_IMSK);
		sky2_write32(hw, B0_IMSK, 0);
		sky2_read32(hw, B0_IMSK);

		dev->trans_start = jiffies; /* prevent tx timeout */
		napi_disable(&hw->napi);
		@@ -3487,8 +3488,8 @@ static void sky2_all_down(struct sky2_hw *hw)
		int i;

		if (hw->flags & SKY2_HW_IRQ_SETUP) {
		sky2_read32(hw, B0_IMSK);
		sky2_write32(hw, B0_IMSK, 0);
		sky2_read32(hw, B0_IMSK);

		synchronize_irq(hw->pdev->irq);
		napi_disable(&hw->napi);