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Commit ea537363 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'amlogic-dt64-2-1' of...

Merge tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Amlogic 64-bit DT changes for v4.19, round 2
- new SoC: S905W
- new boards: based on S905W: Amlogic P281, Oranth Tanix TX3 Mini
- AXG: add DT for new audio clock controller

* tag 'amlogic-dt64-2-1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic

:
  ARM64: dts: meson-gxl: add support for the Oranth Tanix TX3 Mini
  ARM64: dts: meson-gxl: add support for the S905W SoC and the P281 board
  dt-bindings: arm: amlogic: Add support for the Oranth Tanix TX3 Mini
  dt-bindings: arm: amlogic: Add support for GXL S905W and the P281 board
  dt-bindings: add vendor prefix for Shenzhen Oranth Technology Co., Ltd.
  ARM64: dts: meson-axg: add the audio clock controller
  clk: meson: expose GEN_CLK clkid
  clk: meson-axg: add pcie and mipi clock bindings
  dt-bindings: clock: add meson axg audio clock controller bindings

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 295d44ae aaa080fa
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@@ -45,6 +45,10 @@ Boards with the Amlogic Meson GXL S805X SoC shall have the following properties:
  Required root node property:
    compatible: "amlogic,s805x", "amlogic,meson-gxl";

Boards with the Amlogic Meson GXL S905W SoC shall have the following properties:
  Required root node property:
    compatible: "amlogic,s905w", "amlogic,meson-gxl";

Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
  Required root node property:
    compatible: "amlogic,s912", "amlogic,meson-gxm";
@@ -85,6 +89,9 @@ Board compatible values (alphabetically, grouped by SoC):

  - "amlogic,p241" (Meson gxl s805x)

  - "amlogic,p281" (Meson gxl s905w)
  - "oranth,tx3-mini" (Meson gxl s905w)

  - "amlogic,q200" (Meson gxm s912)
  - "amlogic,q201" (Meson gxm s912)
  - "khadas,vim2" (Meson gxm s912)
+56 −0
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* Amlogic AXG Audio Clock Controllers

The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.

Required Properties:

- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D
- reg		: physical base address of the clock controller and length of
		  memory mapped region.
- clocks	: a list of phandle + clock-specifier pairs for the clocks listed
		  in clock-names.
- clock-names	: must contain the following:
		  * "pclk" - Main peripheral bus clock
		  may contain the following:
		  * "mst_in[0-7]" - 8 input plls to generate clock signals
		  * "slv_sclk[0-9]" - 10 slave bit clocks provided by external
				      components.
		  * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
				       components.
- resets	: phandle of the internal reset line
- #clock-cells	: should be 1.

Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.

Example:

clkc_audio: clock-controller@0 {
	compatible = "amlogic,axg-audio-clkc";
	reg = <0x0 0x0 0x0 0xb4>;
	#clock-cells = <1>;

	clocks = <&clkc CLKID_AUDIO>,
		 <&clkc CLKID_MPLL0>,
		 <&clkc CLKID_MPLL1>,
		 <&clkc CLKID_MPLL2>,
		 <&clkc CLKID_MPLL3>,
		 <&clkc CLKID_HIFI_PLL>,
		 <&clkc CLKID_FCLK_DIV3>,
		 <&clkc CLKID_FCLK_DIV4>,
		 <&clkc CLKID_GP0_PLL>;
	clock-names = "pclk",
		      "mst_in0",
		      "mst_in1",
		      "mst_in2",
		      "mst_in3",
		      "mst_in4",
		      "mst_in5",
		      "mst_in6",
		      "mst_in7";
	resets = <&reset RESET_AUDIO>;
};
+1 −0
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@@ -273,6 +273,7 @@ opalkelly Opal Kelly Incorporated
opencores	OpenCores.org
openrisc	OpenRISC.io
option	Option NV
oranth	Shenzhen Oranth Technology Co., Ltd.
ORCL	Oracle Corporation
orisetech	Orise Technology
ortustech	Ortus Technology Co., Ltd.
+2 −0
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@@ -18,6 +18,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
+36 −0
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@@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
@@ -155,6 +156,41 @@
			};
		};

		audio: bus@ff642000 {
			compatible = "simple-bus";
			reg = <0x0 0xff642000 0x0 0x2000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;

			clkc_audio: clock-controller@0 {
				compatible = "amlogic,axg-audio-clkc";
				reg = <0x0 0x0 0x0 0xb4>;
				#clock-cells = <1>;

				clocks = <&clkc CLKID_AUDIO>,
					 <&clkc CLKID_MPLL0>,
					 <&clkc CLKID_MPLL1>,
					 <&clkc CLKID_MPLL2>,
					 <&clkc CLKID_MPLL3>,
					 <&clkc CLKID_HIFI_PLL>,
					 <&clkc CLKID_FCLK_DIV3>,
					 <&clkc CLKID_FCLK_DIV4>,
					 <&clkc CLKID_GP0_PLL>;
				clock-names = "pclk",
					      "mst_in0",
					      "mst_in1",
					      "mst_in2",
					      "mst_in3",
					      "mst_in4",
					      "mst_in5",
					      "mst_in6",
					      "mst_in7";

				resets = <&reset RESET_AUDIO>;
			};
		};

		cbus: bus@ffd00000 {
			compatible = "simple-bus";
			reg = <0x0 0xffd00000 0x0 0x25000>;
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