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Commit e9ed3a67 authored by Emily Deng's avatar Emily Deng Committed by Alex Deucher
Browse files

drm/amdgpu: Define virtual display ip blocks. 



For virtual display feature, define virtual display ip blocks, and set
dce_virtual_ip_funcs to DCE block.

Signed-off-by: default avatarEmily Deng <Emily.Deng@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 048a5b76

drivers/gpu/drm/amd/amdgpu/cik.c

+341 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 


#include "amdgpu_amdkfd.h"

#include "amdgpu_powerplay.h"

#include "dce_virtual.h"



/*

 * Indirect registers accessor
@@ -1708,6 +1709,74 @@ static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 8,

		.minor = 2,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 7,

		.minor = 2,

		.rev = 0,

		.funcs = &gfx_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_sdma_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 4,

		.minor = 2,

		.rev = 0,

		.funcs = &uvd_v4_2_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v2_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1776,6 +1845,74 @@ static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 8,

		.minor = 5,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 7,

		.minor = 3,

		.rev = 0,

		.funcs = &gfx_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_sdma_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 4,

		.minor = 2,

		.rev = 0,

		.funcs = &uvd_v4_2_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v2_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version kabini_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1844,6 +1981,74 @@ static const struct amdgpu_ip_block_version kabini_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 8,

		.minor = 3,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 7,

		.minor = 2,

		.rev = 0,

		.funcs = &gfx_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_sdma_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 4,

		.minor = 2,

		.rev = 0,

		.funcs = &uvd_v4_2_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v2_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version mullins_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1912,6 +2117,74 @@ static const struct amdgpu_ip_block_version mullins_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 8,

		.minor = 3,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 7,

		.minor = 2,

		.rev = 0,

		.funcs = &gfx_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_sdma_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 4,

		.minor = 2,

		.rev = 0,

		.funcs = &uvd_v4_2_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v2_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1980,6 +2253,74 @@ static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 1,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 8,

		.minor = 1,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 7,

		.minor = 1,

		.rev = 0,

		.funcs = &gfx_v7_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &cik_sdma_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 4,

		.minor = 2,

		.rev = 0,

		.funcs = &uvd_v4_2_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v2_0_ip_funcs,

	},

};



int cik_set_ip_blocks(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {

drivers/gpu/drm/amd/amdgpu/vi.c

+282 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ 
#if defined(CONFIG_DRM_AMD_ACP)

#include "amdgpu_acp.h"

#endif

#include "dce_virtual.h"



MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");

MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
@@ -890,6 +891,74 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vi_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &tonga_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 1,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 10,

		.minor = 0,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &sdma_v3_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 5,

		.minor = 0,

		.rev = 0,

		.funcs = &uvd_v5_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v3_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version fiji_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -958,6 +1027,74 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vi_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 8,

		.minor = 5,

		.rev = 0,

		.funcs = &gmc_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &tonga_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 1,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 10,

		.minor = 1,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &sdma_v3_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &uvd_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v3_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1026,6 +1163,74 @@ static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = 
	},

};



static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vi_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 8,

		.minor = 1,

		.rev = 0,

		.funcs = &gmc_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 3,

		.minor = 1,

		.rev = 0,

		.funcs = &tonga_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 7,

		.minor = 2,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 11,

		.minor = 2,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 3,

		.minor = 1,

		.rev = 0,

		.funcs = &sdma_v3_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 6,

		.minor = 3,

		.rev = 0,

		.funcs = &uvd_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 3,

		.minor = 4,

		.rev = 0,

		.funcs = &vce_v3_0_ip_funcs,

	},

};



static const struct amdgpu_ip_block_version cz_ip_blocks[] =

{

	/* ORDER MATTERS! */
@@ -1103,6 +1308,83 @@ static const struct amdgpu_ip_block_version cz_ip_blocks[] = 
#endif

};



static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =

{

	/* ORDER MATTERS! */

	{

		.type = AMD_IP_BLOCK_TYPE_COMMON,

		.major = 2,

		.minor = 0,

		.rev = 0,

		.funcs = &vi_common_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GMC,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gmc_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_IH,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &cz_ih_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SMC,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &amdgpu_pp_ip_funcs

	},

	{

		.type = AMD_IP_BLOCK_TYPE_DCE,

		.major = 11,

		.minor = 0,

		.rev = 0,

		.funcs = &dce_virtual_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_GFX,

		.major = 8,

		.minor = 0,

		.rev = 0,

		.funcs = &gfx_v8_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_SDMA,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &sdma_v3_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_UVD,

		.major = 6,

		.minor = 0,

		.rev = 0,

		.funcs = &uvd_v6_0_ip_funcs,

	},

	{

		.type = AMD_IP_BLOCK_TYPE_VCE,

		.major = 3,

		.minor = 0,

		.rev = 0,

		.funcs = &vce_v3_0_ip_funcs,

	},

#if defined(CONFIG_DRM_AMD_ACP)

	{

		.type = AMD_IP_BLOCK_TYPE_ACP,

		.major = 2,

		.minor = 2,

		.rev = 0,

		.funcs = &acp_ip_funcs,

	},

#endif

};



int vi_set_ip_blocks(struct amdgpu_device *adev)

{

	switch (adev->asic_type) {