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NVIDIA's Tegra has multiple UART controller which supports: - APB DMA based controller fifo read/write. - End Of Data interrupt in incoming data to know whether end of frame achieve or not. - HW controlled RTS and CTS flow control to reduce SW overhead. Add serial driver to use all above feature. Signed-off-by:Laxman Dewangan <ldewangan@nvidia.com> Acked-by:
Alan Cox <alan@linux.intel.com> Reviewed-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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