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Commit e9cd973f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-v3-semi' into next 

* pci/host-v3-semi:
  PCI: v3-semi: Add V3 Semiconductor PCI host driver
  PCI: v3: Update the device tree bindings
parents 29d0d441 68a15eb7

Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt

+68 −7
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@@ -2,14 +2,75 @@ V3 Semiconductor V360 EPC PCI bridge 


This bridge is found in the ARM Integrator/AP (Application Platform)



Integrator-specific notes:

Required properties:

- compatible: should be one of:

  "v3,v360epc-pci"

  "arm,integrator-ap-pci", "v3,v360epc-pci"

- reg: should contain two register areas:

  first the base address of the V3 host bridge controller, 64KB

  second the configuration area register space, 16MB

- interrupts: should contain a reference to the V3 error interrupt

  as routed on the system.

- bus-range: see pci.txt

- ranges: this follows the standard PCI bindings in the IEEE Std

  1275-1994 (see pci.txt) with the following restriction:

  - The non-prefetchable and prefetchable memory windows must

    each be exactly 256MB (0x10000000) in size.

  - The prefetchable memory window must be immediately adjacent

    to the non-prefetcable memory window

- dma-ranges: three ranges for the inbound memory region. The ranges must

  be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,

  64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked

  as pre-fetchable. Two ranges are supported by the hardware.



- syscon: should contain a link to the syscon device node (since

Integrator-specific required properties:

- syscon: should contain a link to the syscon device node, since

  on the Integrator, some registers in the syscon are required to

  operate the V3).

  operate the V3 host bridge.



V360 EPC specific notes:

Example:



- reg: should contain the base address of the V3 adapter.

- interrupts: should contain a reference to the V3 error interrupt

  as routed on the system.
 
pci: pciv3@62000000 {

	compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";

	#interrupt-cells = <1>;

	#size-cells = <2>;

	#address-cells = <3>;

	reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;

	interrupt-parent = <&pic>;

	interrupts = <17>; /* Bus error IRQ */

	clocks = <&pciclk>;

	bus-range = <0x00 0xff>;

	ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */

		0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */

		0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */

		0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */

		0x42000000 0 0x50000000 /* prefetchable memory @50000000 */

		0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */

	dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */

		0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */

		0x02000000 0 0x80000000 /* Core module alias memory */

		0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */

	interrupt-map-mask = <0xf800 0 0 0x7>;

	interrupt-map = <

	/* IDSEL 9 */

	0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */

	0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */

	0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */

	0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */

	/* IDSEL 10 */

	0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */

	0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */

	0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */

	0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */

	/* IDSEL 11 */

	0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */

	0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */

	0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */

	0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */

	/* IDSEL 12 */

	0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */

	0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */

	0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */

	0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */

	>;

};

MAINTAINERS

+7 −0
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@@ -10511,6 +10511,13 @@ S: Maintained 
F:	Documentation/devicetree/bindings/pci/rockchip-pcie.txt

F:	drivers/pci/host/pcie-rockchip.c



PCI DRIVER FOR V3 SEMICONDUCTOR V360EPC

M:	Linus Walleij <linus.walleij@linaro.org>

L:	linux-pci@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt

F:	drivers/pci/host/pci-v3-semi.c



PCIE DRIVER FOR ST SPEAR13XX

M:	Pratyush Anand <pratyush.anand@gmail.com>

L:	linux-pci@vger.kernel.org

drivers/pci/host/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -95,6 +95,12 @@ config PCI_XGENE_MSI 
	  Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.

	  This MSI driver supports 5 PCIe ports on the APM X-Gene v1 SoC.



config PCI_V3_SEMI

	bool "V3 Semiconductor PCI controller"

	depends on OF

	depends on ARM

	default ARCH_INTEGRATOR_AP



config PCI_VERSATILE

	bool "ARM Versatile PB PCI controller"

	depends on ARCH_VERSATILE

drivers/pci/host/Makefile

+1 −0
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@@ -9,6 +9,7 @@ obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o 
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o

obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o

obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o

obj-$(CONFIG_PCI_V3_SEMI) += pci-v3-semi.o

obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o

obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o

obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o

drivers/pci/host/pci-v3-semi.c

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