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Commit e9983344 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm/radix: Add partition table format & callback 



Add structs and #defines related to the radix MMU partition table
format. We also add a ppc_md callback for updating a partition table
entry.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 11a6f6ab

arch/powerpc/include/asm/book3s/64/mmu.h

+29 −2
Original line number Diff line number Diff line
@@ -21,12 +21,39 @@ struct mmu_psize_def { 
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#endif /* __ASSEMBLY__ */



#ifdef CONFIG_PPC_STD_MMU_64

/* 64-bit classic hash table MMU */

#include <asm/book3s/64/mmu-hash.h>

#endif



#ifndef __ASSEMBLY__

/*

 * ISA 3.0 partiton and process table entry format

 */

struct prtb_entry {

	__be64 prtb0;

	__be64 prtb1;

};

extern struct prtb_entry *process_tb;



struct patb_entry {

	__be64 patb0;

	__be64 patb1;

};

extern struct patb_entry *partition_tb;



#define PATB_HR		(1UL << 63)

#define PATB_GR		(1UL << 63)

#define RPDB_MASK	0x0ffffffffffff00fUL

#define RPDB_SHIFT	(1UL << 8)

/*

 * Limit process table to PAGE_SIZE table. This

 * also limit the max pid we can support.

 * MAX_USER_CONTEXT * 16 bytes of space.

 */

#define PRTB_SIZE_SHIFT	(CONTEXT_BITS + 4)

/*

 * Power9 currently only support 64K partition table size.

 */

#define PATB_SIZE_SHIFT	16



typedef unsigned long mm_context_id_t;

struct spinlock;

arch/powerpc/include/asm/machdep.h

+1 −0
Original line number Diff line number Diff line
@@ -256,6 +256,7 @@ struct machdep_calls { 
#ifdef CONFIG_ARCH_RANDOM

	int (*get_random_seed)(unsigned long *v);

#endif

	int (*update_partition_table)(u64);

};



extern void e500_idle(void);

arch/powerpc/include/asm/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -587,6 +587,7 @@ 
#define SPRN_PIR	0x3FF	/* Processor Identification Register */

#endif

#define SPRN_TIR	0x1BE	/* Thread Identification Register */

#define SPRN_PTCR	0x1D0	/* Partition table control Register */

#define SPRN_PSPB	0x09F	/* Problem State Priority Boost reg */

#define SPRN_PTEHI	0x3D5	/* 981 7450 PTE HI word (S/W TLB load) */

#define SPRN_PTELO	0x3D6	/* 982 7450 PTE LO word (S/W TLB load) */