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Commit e952ca3c authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL 



The audio blocks require specific clock rates. Until now we were using
the closest clock rate possible with integer N-M factors. This resulted
in audio playback being slightly slower than it should be.

The vendor kernel gets around this (for newer SoCs) by using sigma-delta
modulation to generate a fractional-N factor. This patch copies the
parameters for the A83T.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 10e6eb4f

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+10 −1
Original line number Diff line number Diff line
@@ -76,17 +76,26 @@ static struct ccu_mult pll_c1cpux_clk = { 
 */

#define SUN8I_A83T_PLL_AUDIO_REG	0x008



/* clock rates doubled for post divider */

static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },

	{ .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },

};



static struct ccu_nm pll_audio_clk = {

	.enable		= BIT(31),

	.lock		= BIT(2),

	.n		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),

	.m		= _SUNXI_CCU_DIV(0, 6),

	.fixed_post_div	= 2,

	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),

					 0x284, BIT(31)),

	.common		= {

		.reg		= SUN8I_A83T_PLL_AUDIO_REG,

		.lock_reg	= CCU_SUN8I_A83T_LOCK_REG,

		.features	= CCU_FEATURE_LOCK_REG |

				  CCU_FEATURE_FIXED_POSTDIV,

				  CCU_FEATURE_FIXED_POSTDIV |

				  CCU_FEATURE_SIGMA_DELTA_MOD,

		.hw.init	= CLK_HW_INIT("pll-audio", "osc24M",

					      &ccu_nm_ops, CLK_SET_RATE_UNGATE),

	},